WM8232 datasheet(35/141 Pages) CIRRUS

номер детали	WM8232

подробное описание детали	105MSPS 3-Channel AFE with Sensor

PDF	141 Pages

Scroll/Zoom	100%

производитель	CIRRUS [Cirrus Logic]

домашняя страница	http://www.cirrus.com

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35 / 141 page

WM8232

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R176 (B0h)

– R177 (B1h)

5:0

DEL_PCK*[1:0]

control delay for pulse output

00 = 0nsec, 01 = 1nsec, 10 = 2nsec, 11 = 3nsec

R135 (81h)

– R146 (92h)

5:0

CLK*_RISE[5:0]

CLK* rise edge (0 to 59)

5:0

CLK*_FALL[5:0]

CLK* fall edge (0 to 59)

TG MASTER MODE OPERATION

In master mode, line length is defined by LLENGTH register.

master

L=LLENGTH[14:0]

Datatrig(Internal)

Datatrig

(LVDS/CMOS output)

TGCK

TGEN(Serial I/F)

Pixel counter

TGSYNC(Output)

tTRIGD

pixcnt=0

POn(Internal)

CLKn(TG pulse out)

FLAGPIX=P1

TPn=P1

TPm=P2

tPCKD

PO_ Flag

(LVDS/CMOS out)

tTRIGD

VSMP

TGCK

2*tPER/60

VSMP

Figure 22 Master Mode Pixel Counter and Line Start Timing

TG SLAVE MODE OPERATION

In slave mode, line length depends on TGSYNC input. The pixel counter is reset by TGSYNC input.

slave

TGSYNC(Input)

32767

tTRIGD

TGCK

TGEN(Serial I/F)

Linestart(Internal)

Pixel counter

tCOUNTD

pixcnt=0

Q=OFFSET[3:0]

FLAGPIX=P1

tSCKSY

TGCK

TGSYNC

tSYH

Flag(Internal)

Flag

(LVDS/CMOS out)

TPn=P1

POn(Internal)

TPm=P2

CLKn(TG pulse out)

tPCKD

PO_Flag

(LVDS/CMOS out)

tTRIGD

VSMP

2*tPER/60

VSMP

tSYH

tSYL

Figure 23 Slave Mode Pixel Counter and Line Start Timing

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