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WM8232 датащи(PDF) 12 Page - Cirrus Logic |
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WM8232 датащи(HTML) 12 Page - Cirrus Logic |
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12 / 141 page ![]() WM8232 12 Rev 4.6 SIGNAL TIMING REQUIREMENTS SERIAL CONTROL INTERFACE SDO (output) tDL SEN (input) SCK (input) SDI (input) tCSU tSCH tSCL tSCY tDHO tDSU tCHO Figure 3 Serial Interface Timing PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SEN falling edge to SCK rising edge tCSU 20 ns SCK falling edge to SEN rising edge tCHO 20 ns SCK pulse cycle time tSCY 83.3 ns SCK pulse width low tSCL 33 ns SCK pulse width high tSCH 33 ns SDI to SCK set-up time tDSU 20 ns SDI to SCK hold time tDHO 20 ns SCK falling edge to SDO transition tDL 33 ns The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin SDO. It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values. DEVICE IDENTIFICATION Up to 4 WM8232 devices can share a common set of serial interface pins. Each device on the common interface bus must be given a different device ID. The device ID is set by the input pin DSLCT2 and DSLCT1 as shown in Table 2. DSLCT2 DSLCT1 DEVICE ID (ID[1:0]) L L 00 L H 01 H L 10 H H 11 Table 2 Device Identification |
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