WM8232 datasheet(57/141 Pages) CIRRUS

57 / 141 page

WM8232

Rev 4.6

TG CLOCK CONFIGURATION

Figure 48 shows the procedure for TG Clock Timing and Mask Configuration. CLK1~CLK6 can be

configured as clock type output. See

“Sensor Timing Generation” section for details of TG function.

TG enabled: This must be enabled when TG mask function is used.

Mask period configuration: TG clock will be masked while mask signal is high.

The rising and

falling timing is configured by M*_RISE/FALL register. See

“TG Mask Timing” section for details of this

function

Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).

TP* register consists of toggle point setting bit (TP value bit) and enable bit. The enable bit must be

set when TP is used. Unused TP can be disabled, but it must be followed Note-2 as described below.

T1 and T2 polarity configuration: T1 and T2 are internal signal to set the TG signal polarity during

mask period. See

“TG Mask Timing” section for details of this function.

TG Clock configuration

CLK1~6 rise/fall timing

configuration

0x87~0x92

CLK*_RISE/FALL

Using TG Mask

function

Line length

configuration

enabled

0xA1,0xA2 LLENGTH

0xA0[0] TG_EN

TG mode

selection

Master mode

0xA0[1] TGMD=1

Slave mode

0xA0[1] TGMD=0

TG enabled (*1)

Yes

Toggle point

Configuration (*2)

0xCF~0x10E TP0~TP31

T1 and T2 polarity

configuration

0x10F~0x116 POL*_T*

Mask configuration

Mask period

configuration

0xC3~0xCE

M*_RISE/FALL

Using T1,T2

function

Yes

Toggle setting for

M1 and M2 period

CLK pin

enabled

0xA5~0xA6 OE_CK*=1

TG signal output

enabled

0xA9~0xAA EN_CK*=1

TG output enabled

Figure 48 TG Clock Configuration

Notes:

This must be set when the TG-MASK function is used.

When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel

counter value must be set as TP0<TP1<TP2 …..

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