WM8232 datasheet(20/141 Pages) CIRRUS

20 / 141 page

WM8232

Rev 4.6

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset

DAC to compensate for offsets and then amplified by a 12-bit PGA. The gain and offset for each

channel are independently programmable by writing to control bits DACINP[7:0] for the Offset DAC,

and AGAIN[4:0] and DGAIN[11:0] for the PGA.

The gain characteristic of the WM8232 PGA is shown in Figure 14.

3.0

5.4

GAIN CODE (AGAIN[4:0])

0.6

7.8

9.9

9.9V/V

0.6V/V

32step

1024

2048

3072

4095

1.0

1.99

GAIN CODE (DGAIN[11:0])

0.5

1.99V/V

0.5V/V

3072

step

APGA = 0.6 + 0.3 * AGAIN[4:0]

DPGA = DGAIN[11:0] / 2^11

Total Gain Range

0.3V/V≦ APGA*DPGA ＜ 19.8V/V

Figure 14 PGA Gain Characteristic

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA can be offset to match the full-scale range of the differential ADC

(1.5*[VREF1C-VREF3C]).

For negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS=0. For positive going input signals

the black level should be offset to the bottom of the ADC range by setting PGAFS=1.

1.33V

2.0V

VRLC/VBIAS

VIN (INPx)

PGAFS= 0, PGA gain=0.9V/V, Offset = 0V

Output code

= (VRLC - VIN) * Gain * 65535/(1.5*[VREF1C-VREF3C])

OP=0

OP=65535

OP=32768

VRLC/VBIAS

VIN (INPx)

PGAFS= 1, PGA gain=0.9V/V, Offset = 0V

Output code

= (VIN - VRLC) * Gain * 65535/(1.5*[VREF1C-VREF3C])

OP=0

OP=65535

OP=32768

1.33V

2.0V

Figure 15 ADC Input Black Level Adjust Settings

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