WM8232 datasheet(17/141 Pages) CIRRUS

17 / 141 page

WM8232

Rev 4.6

DEVICE DESCRIPTION

INTRODUCTION

A block diagram of the device showing the signal path is presented on the front page of this

datasheet.

The WM8232 samples up to three inputs (IN1, IN2 and IN3) simultaneously. The device then

processes the sampled video signal with respect to the video reset level or an internally/externally

generated reference level using between one and six processing channels.

Each processing channel consists of an Input Sampling block with optional Reset Level Clamping

(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 12-bit

Programmable Gain Amplifier (PGA).

The ADC then converts each resulting analogue signal to a digital word. The digital output from the

ADC is presented in a variety of possible output formats in LVDS and CMOS format.

On-chip control registers determine the configuration of the device, including the offsets and gains

applied to each channel. These registers are programmable via a serial interface.

The device has an automatic Black-Level Calibration function which allows the D.C. offset determined

during the optically-black pixels at the beginning of the linear sensor to be removed during the image-

pixels.

The WM8232 also has an Automatic Gain Control function which automatically adjusts the gain to an

appropriate level for a detected input level.

The device incorporates a sensor timing generation function which allows CCD and CMOS sensor

timing to be controlled directly from the device using internal clock generation and register settings.

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the WM8232 lies within the supply voltage range (0V to AVDD),

the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC

circuit clamps the WM8232 side of this capacitor to a suitable voltage through a CMOS switch during

the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping

to produce correct results the input voltage during the clamping must be a constant value.

Note that if the A.C. coupling capacitor (CIN) is used in non-CDS mode (CDS=0), then to minimise

code drift, line clamping should be used and internal input voltage buffers enabled using the SF_INP

and SF_VRLC register bit. Alternatively, if the input signal contains a stable reference/reset level, then

pixel clamping should be used, and the voltage buffers need not be enabled.

The WM8232 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 10.

This figure shows a single channel; however, all 3 channels are identical, each with its own clamp

switch controlled by the common CLMP signal.

The method of control chosen depends upon the characteristics of the input video. The VRLCEN

default VRLCEN=1).

Note that unused inputs should be left floating, or grounded through a decoupling capacitor, if reset

level clamping is used.

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