WM8232 datasheet(23/141 Pages) CIRRUS

23 / 141 page

WM8232

Rev 4.6

PLL DLL SETUP

WM8232 is supporting wide range of input frequency. PLL_EXDIV_SEL[2:0], LVDLGAIN[1:0] and

DLGAIN[1:0] must be configured by MCLK clock rate and data output format.

Note that after PLL and DLL configuration, the device must be reset as the following step.



R03[1:0]=11 (PDMD=1, PD=1)



Delay 1ms



R03[1:0]=00 (Normal operation)

Also, several LVDS operation mode is required to change internal LDO configuration to perform LVDS

clocking properly. The following register need to set to change the LDO configuration.



R1B0h=1



R1B4h=12h

Max sample rate

MCLK Clock rate

[MHz]

30.1

35.0

25.0

29.9

15.0

23.3

12.5

14.99

10.0

12.49

8.33

9.99

7.5

8.32

5.0

7.49

PLL_EXDIV_SEL[2:0]

000

001

010

LVDLGAIN[1:0]

DLGAIN[1:0]

LDO setting

PLL_EXDIV_SEL[2:0]

001

010

011

100

LVDLGAIN[1:0]

DLGAIN[1:0]

LDO setting

PLL_EXDIV_SEL[2:0]

000

001

010

LVDLGAIN[1:0]

DLGAIN[1:0]

LDO setting

12h

PLL_EXDIV_SEL[2:0]

001

010

LVDLGAIN[1:0]

DLGAIN[1:0]

LDO setting

12h

CMOS 10 bit

LVDS 5pair 10bit

LVDS 5pair 16bit

LVDS 4pair 12bit

LVDS 3pair 10bit

LVDS 3pair 16bit

23.3MHz

35MHz

30MHz

Table 4 PLL and DLL Setting

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