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WM8232 датащи(PDF) 140 Page - Cirrus Logic

номер детали WM8232
подробное описание детали  105MSPS 3-Channel AFE with Sensor
PDF  141 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8232 датащи(HTML) 140 Page - Cirrus Logic

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WM8232
140
Rev 4.6
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
PAGE
15/11/10
1.0
AA/NB
First Release
08/12/11
3.0
JMacD
Product status updated to pre-production.
11/12/11
3.0
AA
Updated DAC description 4-bit to 8bit
Updated temperature range to -40
Updated ADCFS characteristics
Updated RLC DAC resolution
Updated Parameter name and Register name for RLC DAC
Added test condition for TG output
Updated Supply currents
Updated diagram of LVDS format
Updated Clamp timing diagram
Updated Signal flow summary (removed INVOP description)
Updated Channel ID description INP to IN
Updated TG MASK description
Updated Register Map (ADCFS)
Updated C9 value
1
5,8
9,10
10
10,39
11
11
18,20
25
28
31
35
39,45
112
14/12/12
4.0
AA
Added channel to channel offset matching specification
Corrected offset DAC INL DNL spec
Corrected supply current for full power down mode
Updated timing specification
Corrected figure for ADC INPUT BLACK LEVEL ADJUST
Corrected figure for overall signal flow
Added description for ADC, PGA Bias Current Control.
Added description for PLL DLL setup
Added description for 3pair and 4pair LVDS format
Added LVDS output order
Corrected TG timing diagram
Added EXTENDED REGISTERES
Corrected description for R28
Corrected description for R128,R129
9
10
11
15,17,33-35
21
22
22
23
27-29
30
32-35
51,118
62
70
17/02/14
4.1
AA
Corrected description of conversion rate
Corrected description of reference DAC resolution
Corrected spec of conversion rate per channel
Updated test condition for output noise specification
Corrected device ID descriptions (Table 2 and Table 3)
Corrected RESET CLAMPING description
Corrected CDS/Non-CDS PROCESSING description
Corrected ADC INPUT BLACK LEVEL ADJUST description
Updated PLL and DLL setting table
Corrected TG-master/slave mode timing chart
Added TGSYNC low period specification
Added description for LINE BY LINE operation
Added description for TEST PATTERN GENERATOR
Added description for Register setting procedure
1
1
9
9
13,14
18,19
20
21
23
35,36
36
48,58,74
49,50,71,72
51~57



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