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PC97307 датащи(PDF) 197 Page - National Semiconductor (TI) |
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PC97307 датащи(HTML) 197 Page - National Semiconductor (TI) |
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197 / 218 page ![]() 197 Device Description www.national.com 13.3.6 Receiver Timing TABLE 13-40. Receiver Timing FIGURE 13-8. Receiver Timing a. Not tested. Guaranteed by design. b. This is internal timing and is therefore not tested. Symbol Parameter Conditions Min Max Unit tIRRXW IRRX Pulse Width a 1.6 µsec 6/ 16 Baud Output Cycles tRAI1 Delay from Active Edge of RD to Reset IRQ 78 nsec tRAI2 Delay from Active Edge of RD to Reset IRQ 78 nsec tRAI3 Delay from Active Edge of RD to Reset IRQ 78 nsec tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 nsec tSCD Delay from RCLK to Sample Time b 41 nsec tSINT Delay from Stop bit to Set Interrupt a 2 Baud Output Cycles RCLK Sample CLK SIN Sample Clock RDR LSI RD (RDRBR) RD (RD LSR) Interrupt Interrupt tSINT tRINT tRAI1 tSCD 8 CLKS DATA (5-8) STOP ACTIVE ACTIVE IRRX tIRRXW |
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