MCP39F521 datasheet(16/52 Pages) MICROCHIP

16 / 52 page

MCP39F521

DS20005442A-page 16

 2015 Microchip Technology Inc.

This approach allows for single, secure transmission

from the host processor to the MCP39F521 with either

single

command,

multiple

commands.

No command in a frame is processed until the frame is

complete and the checksum and number of bytes are

validated after the stop bit.

The number of bytes in an individual command packet

depends on the specific command. For example, to set

the instruction pointer, three bytes are needed in the

packet: the command byte and two bytes for the

address you want to set to the pointer. The first byte in

a command packet is always the command byte.

4.2

I2C CONTROL BYTE

A Control byte is the first byte received following the

Start condition from the master device. The Control

byte consists of a 4-bit control code. For the

MCP39F521 the control code is ‘1110’ for all read and

write operations. The following three bits are

chip-select address bits, A2, A1, and A0. For the

MCP39F521, A2 is always set to binary ‘1’. A1 and A0

are controlled by the logic pins A1 and A0, which

allows up to 4 different devices on the I2C bus.

The last bit of the Control byte defines the operation to

be performed. When set to ‘1’, a read operation is

selected. When set to ‘0’, a write operation is selected.

Following a Start condition, the MCP39F521 monitors

the SDA bus checking for the 4-bit control code

(‘1110’) and proper address bits. Upon receiving the

correct control code and address bits, the slave

(MCP39F521) outputs an acknowledge signal on the

SDA line, and depending on the state of the R/W bit,

will either respond with data or wait to receive

additional bytes prior to the Stop condition. The

Control byte is defined in the following figure.

FIGURE 4-5:

MCP39F521 Control Byte Format.

4.3

I2C Time Out and Clock Stretching

Time out is when an I2C slave resets its interface if the

I2C clock is low for longer than a specified time. The

MCP39F521 offers a set 2 ms I2C time out that can be

disabled through the Time-out Disable bit in the System

Configuration Register (Register 6-2).

In addition, the device includes a clock stretching

feature which allows the master to know when a frame

has been processed. Clock stretching is when a slave

device can not cooperate with the clock speed or needs

to slow down the bus. In the case of the MCP39F521,

after a frame is received, the device will hold the clock

low until the frame has been processed. The maximum

clock stretching duration is less than 10 milliseconds.

4.4

Checksum

The checksum is generated using simple byte addition

and taking the modulus to find the remainder after

dividing the sum of the entire frame by 256. This

operation is done to obtain an 8-bit checksum. All the

bytes of the frame are included in the checksum,

including the header byte and number of bytes. If a

frame includes multiple command packets, none of the

commands will be issued if the frame checksum fails.

In this instance, the MCP39F521 will respond with a

CSFAIL response of 0x51.

On commands that are requesting data back from the

MCP39F521, the frame and checksum are created in

the same way, with the header byte becoming an

acknowledge (0x06). Communication examples are

given in Section 4.6, Example Communication

Frames and MCP39F521 Responses

1 A1 A0 R/W ACK

Control Code

Chip Select

Bits

Read/Write Bit

Slave Address

Start Bit

Acknowledge Bit

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