MCP39F521 datasheet(22/52 Pages) MICROCHIP

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MCP39F521

DS20005442A-page 22

 2015 Microchip Technology Inc.

5.0

CALCULATION ENGINE (CE)

DESCRIPTION

5.1

Computation Cycle Overview

The MCP39F521 uses a coherent sampling algorithm

to phase lock the sampling rate to the line frequency

with an integer number of samples per line cycle, and

reports all power output quantities at a 2N number of

line cycles. This is defined as a computation cycle and

is dependent on the line frequency, so any change in

the line frequency will change the update rate of the

output power quantities.

5.2

Accumulation Interval Parameter

The accumulation interval is defined as an 2N number

of line cycles, where N is the value in the Accumulation

Interval Parameter register.

5.3

Raw Voltage and Currents Signal

Conditioning

The first set of signal conditioning that occurs inside the

MCP39F521 is shown in Figure 5-1. All conditions set

in this diagram effect all of the output registers

(RMS current, RMS voltage, active power, reactive

power, apparent power, etc.). The gain of the PGA, the

Shutdown and Reset status of the 24-bit ADCs are all

controlled through the System Configuration register

(Register 6-2).

For DC applications, offset can be removed by using

the DC Offset Current register. To compensate for any

external phase error between the current and voltage

channels, the Phase Compensation register can be

used.

See Section 8.0, MCP39F521 Calibration for more

information on device calibration.

FIGURE 5-1:

Channel I1 and V1 Signal Flow.

5.4

RMS Current and RMS Voltage

The

MCP39F521

device

provides

true

RMS

measurements. The MCP39F521 device has two

simultaneous sampling 24-bit A/D converters for the

current and voltage measurements. The root mean

square calculations are performed on 2N current and

voltage samples, where N is defined by the register

Accumulation Interval Parameter.

EQUATION 5-1:

RMS CURRENT AND

VOLTAGE

CHANNEL I1

24-bit

 ADC

Multi-Level

Modulator



DC Offset Current:s16

CHANNEL V1

24-bit

 ADC

Multi-Level

Modulator



PhaseCompensation:s16

PGA

I1+

I1-

PGA

V1+

V1-

SystemConfiguration:b32

Note

High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel.

HPF 1

RMS



–



-----------------------------

RMS



–



------------------------------

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