MCP39F521 datasheet(33/52 Pages) MICROCHIP

33 / 52 page

 2015 Microchip Technology Inc.

DS20005442A-page 33

MCP39F521

bit 11

ZCD_PULS:

Zero Crossing Detection Pulse mode

= ZCD output is 100 µs pulses on zero crossings

= ZCD Output changes logic state on zero crossings (DEFAULT)

bit 10

ZCD_OUTPUT_DIS:

Disable the Zero Crossing output pin

= ZCD output is disabled

= ZCD output is enabled (Default)

bit 9-8

Unimplemented:

Read as ‘0’

bit 7

TEMPCOMP:

temperaure compensation enable bit

= Temperature compensation is enabled

= Temperature compensation is disabled (DEFAULT)

bit 6-5

RESET <1:0>:

Reset mode setting for ADCs

= Both I1 and V1 are in Reset mode

= V1 ADC is in Reset mode

= I1 ADC is in Reset mode

= Neither ADC is in Reset mode (DEFAULT)

bit 4-3

SHUTDOWN <1:0>:

Shutdown mode setting for ADCs

= Both I1 and V1 are in Shutdown

= V1 ADC is in Shutdown

= I1 ADC is in Shutdown

= Neither ADC is in Shutdown (DEFAULT)

bit 2

VREFEXT:

Internal Voltage Reference Shutdown Control

= Internal Voltage Reference Disabled

= Internal Voltage Reference Enabled (DEFAULT)

bit 1-0

Unimplemented:

Read as ‘0’

ENERGY ACCUMULATION CONTROL REGISTER

U-0

—

bit 15

bit 8

U-0

R/W-0

—

ENRG_CNTRL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bits 15-1

Unimplemented:

Read as ‘0‘

bit 0

ENRG_CNTRL:

Energy Accumulation Control bit

= Energy Accumulation is tuned on and all registers are accumulating

= Energy Accumulation is turned off and all energy accumulation registers are reset to 0 (DEFAULT)

SYSTEM CONFIGURATION REGISTER (CONTINUED)

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