MCP39F521 datasheet(31/52 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005442A-page 31

MCP39F521

6.4

System Version Register

The System Version register is hard-coded by

Microchip Technology Inc. and contains calculation

engine date code information. The System Version

and month in hex, day in decimal (e.g. 0xF316 = 2015,

Feb. 16th).

6.5

System Configuration

The System Configuration register (Register 6-2)

contains bits for controlling the following:

• PGA setting

• ADC Reset State

• ADC Shutdown State

• Voltage Reference Trim

• Single Wire Auto-Transmission

These options are described in the following sections.

6.5.1

PROGRAMMABLE GAIN

AMPLIFIERS (PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each 24-bit Delta-Sigma ADC. They

have two functions:

• Translate the Common mode of the input from

AGND to an internal level between AGND and AVDD

• Amplify the input differential signal

The translation of the Common mode does not change

the differential signal but enters the Common mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the delta-sigma

modulator must not be exceeded. The PGA is

controlled by the PGA_CHn<2:0> bits in Register 6-2

the

System

Configuration

Table 6-2

represents the gain settings for the PGAs.

6.5.2

24-BIT ADC RESET MODE

(SOFT RESET MODE)

24-bit ADC Reset mode (also called Soft Reset) can

only be entered through setting high the RESET<1:0>

bits in the System Configuration register (Register 6-2).

This mode is defined as the condition where the

converters are active but their output is forced to ‘0’.

6.5.3

ADC SHUTDOWN MODE

ADC Shutdown mode is defined as a state where the

converters and their biases are OFF, consuming only

leakage current. When the Shutdown bit (SHUTDOWN

<1:0>) is reset to ‘0’, the analog biases will be enabled,

as well as the clock and the digital circuitry.

Each converter can be placed in Shutdown mode

independently. This mode is only available through

programming of the SHUTDOWN<1:0> bits in the

System Configuration register (Register 6-2).

6.5.4

VREF TEMPERATURE

COMPENSATION

If desired, the user can calibrate out the temperature

drift for ultra-low VREF drift.

The internal voltage reference comprises a proprietary

circuit and algorithm to compensate first-order and

second-order

temperature

coefficients.

The

compensation allows very low temperature coefficients

(typically 10 ppm/°C)

on the entire

range of

temperatures from -40°C to +125°C. This temperature

coefficient varies from part to part.

The temperature coefficient can be adjusted on each

part through the System Configuration register

(0x0042) (Register 6-2). The default value of this

temperature coefficient of the internal voltage

reference, with respect to VREFCAL register code, is

shown in Figure 6-1.

FIGURE 6-1:

VREF Tempco vs. VREFCAL

Trimcode Chart.

TABLE 6-2:

PGA CONFIGURATION

SETTING (Note 1)

Gain

PGA_CHn<2:0>

Gain

(V/V)

Gain

(dB)

VIN Range

(V)

±0.5

±0.25

±0.125

±0.0625

±0.03125

±0.015625

Note 1:

The two undefined settings (110, 111)

are G = 1.

128

192

256

VREFCAL Register Trim Code (decimal)

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