MCP39F521 datasheet(11/52 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005442A-page 11

MCP39F521

3.0

PIN DESCRIPTION

The description of the pins are listed in Table 3-1.

3.1

Event Output Pin (EVENT)

This digital output pin can be configured to act as an

output flag based on various internal raise conditions.

Control is modified through the Event Configuration

3.2

Common Pins (COMMONA and

COMMONB)

The COMMONA and COMMONB pins are internal

connections for the MCP39F521. These two pins

should be connected together in the application.

3.3

Oscillator Pins (OSCI/OSCO)

OSCI and OSCO provide the master clock for the

device. Appropriate load capacitance should be

connected to these pins for proper operation. An

optional 4 MHz crystal can be connected to these pins.

If a crystal of external clock source is not detected, the

device will clock from the internal 4 MHz oscillator.

3.4

Reset Pin (RESET)

This pin is active-low and places the delta-sigma

ADCs, PGA, internal VREF and other blocks associated

with the analog front-end in a Reset state when pulled

low. This input is Schmitt-triggered.

TABLE 3-1:

PIN FUNCTION TABLE

MCP39F521

5x5 QFN

Symbol

Function

EVENT

Event Output Pin

2, 3, 8, 9

No Connect (must be left floating)

4COMMONB

Common pin B, to be connected to COMMONA

5COMMONA

Common pin A, to be connected to COMMONB

OSCI

Oscillator Crystal Connection Pin or External Clock Input Pin

OSCO

Oscillator Crystal Connection Pin

RESET

Reset Pin for Delta Sigma ADCs

AVDD

Analog Power Supply Pin

I2C Address Select Pin A0

SCL

I2C Serial Clock

SDA

I2C Serial Data

I2C Address Select Pin A1

I1+

Noninverting Current Channel Input for 24-bit

 ADC

I1-

Inverting Current Channel Input for 24-bit

 ADC

V1-

Inverting Voltage Channel Input for 24-bit

 ADC

V1+

Noninverting Voltage Channel Input for 24-bit

 ADC

AN_IN

Analog Input for SAR ADC

AGND

Analog Ground Pin, Return Path for internal analog circuitry

ZCD

Zero Crossing Detection Output

REFIN+/OUT

Noninverting Voltage Reference Input and Internal Reference Output Pin

24, 27

DGND

Digital Ground Pin, Return Path for internal digital circuitry

DVDD

Digital Power Supply Pin

MCLR

Master Clear for Device

Data Ready (must be left floating)

Exposed Thermal Pad (to be connected to DGND)

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