MCP39F521 datasheet(26/52 Pages) MICROCHIP

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MCP39F521

DS20005442A-page 26

 2015 Microchip Technology Inc.

5.11

10-Bit Analog Input

The least 10 significant bits of the 16-bit Analog Input

conversion rate of the analog input occurs once every

computation cycle.

The Thermistor Voltage can be used for temperature

compensation

the

calculation

engine.

See

Section 8.7, Temperature Compensation

for more

information.

FIGURE 5-6:

Using an Analog

Out-Temperature Sensor for Automatic

Temperature Compensation.

5.12

Minimum and Maximum

Recordings

The MCP39F521 has the ability to record minimum and

maximum outputs and keep them in a total of four

registers (two minimum and two maximum) based on

the value of address pointers located in the four

registers listed below.

A minimum and maximum test is done after each

calculation interval. If the current measurement value

of the value directed to by the pointer is smaller or

larger than the value in the Minimum or Maximum

The registers are listed as follows:

• MinMaxPointer1 → MinimumRecord1,

MaximumRecord1

• MinMaxPointer2 → MinimumRecord2,

MaximumRecord2

Only the output quantity register addresses can be

tracked by the Min/Max pointers. Output quantity

registers are defined as those from Voltage RMS to

Apparent Power (addresses 0x0006 to 0x001A). All

other addresses will be ignored by the calculation

engine.

Please note that the 64-bit energy registers can not be

tracked through the Minimum and Maximum recording

registers.

5.13

Zero Crossing Detection (ZCD)

The Zero Crossing Detection block generates a logic

pulse output on the ZCD pin that is coherent with the

zero crossing of the input AC signal present on voltage

input pins (V1+, V1-). The ZCD pin can be enabled and

disabled

the

corresponding

bit

(ZCD_OUTPUT_DIS) in the System Configuration

square wave with a frequency that is twice that of the

AC signal present on the voltage input. Figure 5-7

represents the signal on the ZCD pin superimposed

with the AC signal present on the voltage input in this

mode.

FIGURE 5-7:

Zero Crossing Detection

Operation (Noninverted, Non-Pulsed).

A second mode is available that produces a

100 µs pulse (ZCD_PULS) at each zero crossing,

shown in Figure 5-8.

FIGURE 5-8:

Zero Crossing Detection

Operation (Noninverted, Pulsed).

Switching modes is done by setting the corresponding

bit in the System Configuration register (Register 6-2).

In addition, either the toggling of this pin, or the pulse,

can be inverted. The ZCD Inversion bit (ZCD_INV) is

also

the

System

Configuration

(Register 6-2).

There are two bits in the System Configuration register

that can be used to modify the zero crossing. The zero

crossing output can be inverted by setting the Inversion

bit, or the zero crossing can be a 100 µs pulse at each

zero crossing, by setting the Pulse Bit.

Note that a low-pass filter is included in the signal path

that allows the zero crossing detection circuit to filter

out

the

fundamental

frequency.

internal

compensation circuit is then used to gain back the

phase delay introduced by the low-pass filter resulting

in a latency of less than 100 µs.

AnalogInput:u16

10-bit

ADC

MCP9700

<100 µs

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