DS3134 datasheet(137/203 Pages) DALLAS

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DS3134

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Transmit Done Queue Internal Address Storage Table 8.2.4A

Acronym

Address

Transmit Done Queue Base Address 0 (lower word)

TDQBA0

0830h

Transmit Done Queue Base Address 1 (upper word)

TDQBA1

0834h

Transmit Done Queue DMA Write Pointer

TDQWP

0840h

Transmit Done Queue Host Read Pointer

TDQRP

083Ch

Transmit Done Queue End Address

TDQEA

0838h

Transmit Done Queue FIFO Flush Timer

TDQFFT

0844h

Note: Transmit Done Queue End Address is not an absolute address. The absolute end address is “Base +

TDQEA * 4”.

Transmit Done Queue Structure Figure 8.2.4B

Once the Transmit DMA is activated (via the TDE control bit in the Master Configuration register; see

Section 4 for more details), it can begin writing data to the Done Queue. It knows where to write data

into the Done Queue by reading the Write Pointer and adding it to the Base Address to obtain the actual

32-bit address. Once the DMA has written to the Done Queue, it increments the Write Pointer by one

dword. A check must be made to make sure the incremented address does not exceed the Transmit Done

Queue End Address. If the incremented address does exceed this address, then the incremented write

pointer will be set equal to 0000h (i.e. the Base Address).

Status Bits / Interrupts

On writes to the Done Queue by the DMA, the DMA will set the Status Bit for Transmit DMA Done

Queue Write (TDQW) in the Status Register for DMA (SDMA). The Host can configure the DMA to

either set this status bit on each write to the Done Queue or only after multiple (from 2 to 128) writes.

The Host controls this by setting the TDQT0 to TDQT2 bits in the Transmit DMA Queues Control

(TDMAQ) register. See the description of the TDMAQ register at the end of this section for more details.

dmatdq

Base + 00h

Base + 04h

Base + 08h

Base + 0Ch

Base + 10h

Base + 14h

Base + End Address

Done Queue DMA Write Pointer

Done Queue Host Read Pointer

Maximum of 65536

Done Queue Descriptors

DMA Readied

Done Queue Descriptor

DMA Readied

Done Queue Descriptor

DMA Readied

Done Queue Descriptor

DMA Readied

Done Queue Descriptor

Host Processed

Done Queue Descriptor

Host Processed

Done Queue Descriptor

Host Processed

Done Queue Descriptor

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