DS3134 datasheet(91/203 Pages) DALLAS

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DS3134

91 of 203

0920h

5432

HCID7

HCID6

HCID5

HCID4

HCID3

HCID2

HCID1

HCID0

IAB

IARW

n/a

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).

00000000 (00h) = HDLC Channel Number 1

11111111 (FFh) = HDLC Channel Number 256

Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal

Receive High Water Mark RAM, this bit should be written to a one by the host. This causes the device to

begin obtaining the data from the channel location indicated by the HCID bits. During the read access,

the IAB bit will be set to one. Once the data is ready to be read from the RFHWM register, the IAB bit

will be set to zero. When the host wishes to write data to the internal Receive High Water Mark RAM,

this bit should be written to a zero by the host. This causes the device to take the data that is currently

present in the RFHWM register and write it to the channel location indicated by the HCID bits. When the

device has completed the write, the IAB will be set to zero.

Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only

bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be

read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set

to a one while the write is taking place. It will be set to zero once the write operation has completed.

RFHWM

0924h

RHWM7

RHWM6

RHWM5

RHWM4

RHWM3

RHWM2

RHWM1

RHWM0

n/a

RHWM9

RHWM8

Note: Bits that are underlined are read only, all other bits are read-write.

Bits 0 to 9 / High Water Mark (RHWM0 to RHWM9). These 10 bits indicate the setting of the

Receive High Water Mark. The High Water Mark setting is the number of successive blocks that the

HDLC engine will write to the FIFO before the DMA will send the data to the PCI Bus. The High Water

Mark setting must be between (inclusive) one block and one less than the number of blocks in the link-list

chain for the particular channel involved. For example, if four blocks are linked together, then the High

Water Mark can be set to 1, 2 or 3. In another words the High Water Mark can be set to a value of 1 to N

– 1, where N = number of blocks are linked together. Any other numbers are illegal.

0000000000 (000h) = invalid setting

0000000001 (001h) = High Water Mark is 1 Block

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