DS3134 datasheet(57/203 Pages) DALLAS

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DS3134

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Bit 6 / Sync Select Bit 0 (RSS0).

Bit 7 / Sync Select Bit 1 (RSS1).

These 2 bits select the mode in which each port is to be operated. Each port can be configured to accept

24, 32, 64, or 128 DS0 channels at an 8 kHz rate. These bits are ignored if the port has been configured

to operate in an unchannelized fashion (RUEN = 1).

00 = T1 Mode (24 DS0 channels & 193 RC clocks in between RS sync signals)

01 = E1 Mode (32 DS0 channels & 256 RC clocks in between RS sync signals)

10 = 4.096 MHz Mode (64 DS0 channels & 512 RC clocks in between RS sync signals)

11 = 8.192 MHz Mode (128 DS0 channels & 1024 RC clocks in between RS sync signals)

Bit 8 / Port 0 High Speed Mode (RP0(1)HS). If enabled, the Port 0(1) Layer State Machine logic is

defeated and RC0(1) and RD0(1) are routed to some dedicated high speed HDLC processing logic. Only

present in RP0CR and RP1CR. Bit 8 is not assigned in Ports 2 through 15.

0 = disabled

1 = enabled

Bit 9 / Unchannelized Enable (RUEN).

When enabled, this bit forces the port to operate in an

unchannelized fashion. When disabled, the port will operate in a channelized mode.

0 = channelized mode

1 = unchannelized mode

Bit 10 / Local Loopback Enable (LLB). This loopback routes transmit data back to the receive port. It

can be used in both channelized and unchannelized port operating modes, even on ports 0 & 1 operating

at speeds up to 52 MHz. See Figure 5.1A. In channelized applications, a per-channel loopback can be

realized by using the Channelized Local LoopBack (CLLB) function. See Section 5.3 for details on

CLLB.

0 = loopback disabled

1 = loopback enabled

Bit 12 / V.54 Time Out (VTO). This read only bit reports the real time status of the V.54 detector. It

will be set to a one when the V.54 detector has finished searching for the V.54 loop up pattern and has not

detected it. This indicates to the Host that the V.54 detector can now be used to search for the V.54 loop

up pattern on other HDLC channels and the Host can initiate this by configuring the RV54 bits in the

RP[n]CR register and then toggling the VRST control bit. See Section 5.4 for more details on how the

V.54 detector operates.

Bit 13 / V.54 Loopback (VLB). This read only bit reports the real time status of the V.54 detector. It

will be set to a one when the V.54 detector has verified that a V.54 loop up pattern has been seen. When

set, it will remain set until either the V.54 loop down pattern is seen or the V.54 detector is reset by the

Host (i.e. by toggling VRST). See Section 5.4 for more details on how the V.54 detector operates.

Bit 14 / Interrupt Enable for RCOFA (IERC).

0 = interrupt masked

1 = interrupt enabled

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