DS3134 datasheet(133/203 Pages) DALLAS

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DS3134

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Transmit Pending Queue Internal Address Storage Table 8.2.3A

Acronym

Address

Transmit Pending Queue Base Address 0 (lower word)

TPQBA0

0800h

Transmit Pending Queue Base Address 1 (upper word)

TPQBA1

0804h

Transmit Pending Queue Host Write Pointer

TPQWP

080Ch

Transmit Pending Queue DMA Read Pointer

TPQRP

0810h

Transmit Pending Queue End Address

TPQEA

0808h

Note: Transmit Free Queue End Address is not an absolute address. The absolute end address is “Base +

TPQEA”.

Transmit Pending Queue Structure Figure 8.2.3B

Once the Transmit DMA is activated (by setting the TDE control bit in the Master Configuration register;

see Section 4), it can begin reading data out of the pending queue. It knows where to read data out of the

pending queue by reading the Read Pointer and adding it to the Base Address to obtain the actual 32-bit

address. Once the DMA has read the Pending Queue, it increments the Read Pointer by one dword. A

check must be made to make sure the incremented address does not exceed the Transmit Pending Queue

End Address. If the incremented address does exceed this address, then the incremented read pointer will

be set equal to 0000h.

Status / Interrupts

On each read of the Pending Queue by the DMA, the DMA will set the Status Bit for Transmit DMA

Pending Queue Read (TPQR) in the Status Register for DMA (SDMA). The status bits can also (if

enabled) cause a hardware interrupt to occur. See Section 4 for more details.

dmatpq

Base + 00h

Base + 04h

Base + 08h

Base + 0Ch

Base + 10h

Base + 14h

Base + End Address

Pending Queue Host Write Pointer

Pending Queue DMA Read Pointer

Maximum of 65536

Pending Queue Descriptors

DMA Acquired

Pending Queue Descriptor

DMA Acquired

Pending Queue Descriptor

DMA Acquired

Pending Queue Descriptor

Host Readied

Pending Queue Descriptor

Host Readied

Pending Queue Descriptor

Host Readied

Pending Queue Descriptor

Host Readied

Pending Queue Descriptor

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