DS3134 datasheet(60/203 Pages) DALLAS

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DS3134

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5.3 LAYER ONE CONFIGURATION REGISTER DESCRIPTION

There are three configuration registers for each DS0 channel on each port. These three registers are

shown in Figure 5.3A. As shown in Figure 5.1A, each of the 16 ports contains a PORT RAM, this

controls the Layer One State Machine. These 384 registers (three registers x 128 DS0 channels per port)

make up the PORT RAM for each port and they control and provide access to the Layer One State

Machine. These registers are accessed indirectly via the Channelized Port Register Data (CP[n]RD)

read. On power-up, the Host must write to all of the used R[n]CFG[j] and T[n]CFG[j] locations to make

sure that they are set into a known state.

LAYER ONE REGISTER SET Figure 5.3A

C[n]DAT[j]: Channelized DS0 Data

lsb

RDATA(8): Receive DS0 Data

msb

TDATA(8): Transmit DS0 Data

R[n]CFG[j]: Receive Configuration

lsb

RCH#(8): Receive HDLC Channel Number

msb

RCHEN

RBERT

n/a

RV54

n/a

CLLB

n/a

R56

T[n]CFG[j]: Transmit Configuration

lsb

TCH#(8): Transmit HDLC Channel Number

msb

TCHEN

TBERT

n/a

CNLB

n/a

TFAO

T56

CP[n]RDIS where n = 0 to 15 for each Port

See the Register Map in Section 3

5432

n/a

CHID6

CHID5

CHID4

CHID3

CHID2

CHID1

CHID0

IAB

IARW

n/a

CPRS1

CPRS0

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bits 0 to 6 / DS0 Channel ID (CHID0 to CHID6). The number of DS0 channels used depends on

whether the port has been configured for an unchannelized application or for a channelized application

and if set for a channelized application, then whether the port has been configured in the T1, E1, 4.096

MHz, or 8.192 MHz mode.

0000000 (00h) = DS0 Channel Number 0

1111111 (7Fh) = DS0 Channel Number 127

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