DS3134 datasheet(135/203 Pages) DALLAS

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DS3134

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Bit 2 / Transmit Done Queue FIFO Enable (TDQFE). See Section 8.2.4 for details.

Bit 3 / Transmit Done Queue FIFO Flush (TDQF). See Section 8.2.4 for details.

Bits 8 to 10 / Transmit Done Queue Status Bit Threshold Setting (TDQT0 to TDQT2). See Section

8.2.4 for more details.

8.2.4 DONE QUEUE

The DMA will write to the Transmit Done Queue when it has finished either transmitting a complete

packet chain or a complete data buffer. This option is selected by the Host when it configures the DQS

field in the Transmit DMA Configuration RAM. See Section 8.2.5 for more details on the Transmit

DMA Configuration RAM. The descriptor location is indicated in the Done Queue via a 16-bit pointer

which the Host will use along with the Transmit Descriptor Base Address to find the exact 32-bit address

of the associated Transmit Descriptor.

Transmit Done Queue Descriptor Figure 8.2.4A

dword 0

unused

Status(3)

CH RST

PRI

HDLC Channel (8)

Descriptor Pointer (16)

Note: The organization of the Done Queue is not affected by the enabling of Big Endian

dword 0; Bits 0 to 15 / Descriptor Pointer. This 16-bit value is the offset from the Transmit Descriptor

Base Address to either the first descriptor in a HDLC packet (can be a single descriptor) that has been

transmitted (DQS = 0) or the descriptor that corresponds to a single data buffer that has been transmitted

(DQS = 1).

dword 0; Bits 16 to 23 / HDLC Channel Number. HDLC channel number, which can be from 1 to

256.

00000000 (00h) = HDLC Channel Number 1

11111111 (FFh) = HDLC Channel Number 256

dword 0; Bit 24 / Priority Packet (PRI). This field is meaningless in the Done Queue and could be set

to any value. See the Pending Queue description in Section 8.2.3 for details.

dword 0; Bit 25 / Channel Reset (CH RST). This field is meaningless in the Done Queue and could be

set to any value. See the Pending Queue description in Section 8.2.3 for details.

dword 0; Bits 26 to 28 / Packet Status. These 3 bits report the final status of an outgoing packet. All

of the error states cause a HDLC abort sequence (8 ones in a row followed by continuous Interfill Bytes of

either FFh or 7Eh) to be sent and the channel will be placed out of service by the transmit DMA setting

the Channel Enable (CHEN) bit in the Transmit DMA Configuration RAM to zero. The status state of

000 will only be used when the channel has been configured by the Host to write to the Done Queue only

after a complete HDLC packet (can be a single data buffer) has been transmitted (i.e. DQS = 0). The

status states of 001, 010, and 011 will only be used when the channel has been configured by the Host to

write to the Done Queue after each data buffer has been transmitted (i.e. DQS = 1).

000 = packet transmission complete and the Descriptor Pointer field corresponds to the first

descriptor in a HDLC packet (can be a single descriptor) that has been transmitted (DQS = 0)

001 = first buffer transmission complete of a multi (or single) buffer packet (DQS = 1)

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