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DS3134 датащи(PDF) 67 Page - Dallas Semiconductor

номер детали DS3134
подробное описание детали  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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производитель  DALLAS [Dallas Semiconductor]
домашняя страница  https://www.maximintegrated.com/en.html
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DS3134 датащи(HTML) 67 Page - Dallas Semiconductor

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Receive V.54 Search Routine Table 5.4A
Step #1: Set Up the Channel Search
The Host will determine in which DS0 channels the V.54 search is to take place by configuring the RV54
bit in the R[n]CFG[j] register. If this search sequence does not detect the V.54 pattern, then the Host can
pick some new DS0 channels and try again.
Step #2: Toggle VRST
Once the DS0 channels have been set, the Host will toggle the VRST bit in the RP[n]CR register and
begin monitoring the SLBP status bit.
Step #3: Wait for SLBP
The SLBP status bit reports any change of state in the V.54 search process. It can also generate a
hardware interrupt, see Section 4 for more details.
When SLBP is set, then the Host knows that
something significant has occurred and that it should read the VLB and VTO real time status bits in the
RP[n]CR register.
Step #4: Read VTO & VLB
If VTO = 1, then the V.54 pattern did not appear in this set of channels and the Host can now reconfigure
the search in other DS0 channels and hence move back to Step #1.
If VLB = 1, then the V.54 loop up pattern has been detected and the channel should be placed into
loopback. A loopback can be invoked by the Host by configuring the CNLB bit in the T[n]CFG[j]
register for each DS0 channel that needs to be placed into loopback. Move back to Step #3.
If VLB = 0, if the DS0 channels are already in loopback, then the Host will monitor VLB to know when
the loop down pattern has been detected and hence when to take the channels out of loopback. The DS0
channels are taken out of loopback by again configuring the CNLB bits. Move on to Step #1.



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