DS3134 datasheet(40/203 Pages) DALLAS

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DS3134

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Bit 0 / Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to zero,

the receive DMA will not pass any data from the receive FIFO to the PCI Bus even if there is one or more

HDLC channels enabled.

On device initialization, the Host should fully configure the receive DMA

before enabling it via this bit.

0 = receive DMA is disabled

1 = receive DMA is enabled

Bit 1 / Receive DMA Throttle Select Bit 0 (RDT0).

Bit 2 / Receive DMA Throttle Select Bit 1 (RDT1).

These two bits select the maximum burst length that the receive DMA is allowed on the PCI Bus. The

DMA can be restricted to a maximum burst length of just 32 dwords (128 bytes) or it can be

incrementally adjusted up to 256 dwords (1024 bytes). The Host will select the optimal length based on a

number of factors including the system environment for the PCI Bus, the number of HDLC channels

being used, and the trade off between channel latency and bus efficiency.

00 = burst length maximum is 32 dwords

01 = burst length maximum is 64 dwords

10 = burst length maximum is 128 dwords

11 = burst length maximum is 256 dwords

Bit 3 / Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to

zero, the transmit DMA will not pass any data from the PCI Bus to the transmit FIFO even if there is one

or more HDLC channels enabled.

On device initialization, the Host should fully configure the transmit

DMA before enabling it via this bit.

0 = transmit DMA is disabled

1 = transmit DMA is enabled

Bit 4 / Transmit DMA Throttle Select Bit 0 (TDT0).

Bit 5 / Transmit DMA Throttle Select Bit 1 (TDT1).

These two bits select the maximum burst length that the transmit DMA is allowed on the PCI Bus. The

DMA can be restricted to a maximum burst length of just 32 dwords (128 bytes) or it can be

incrementally adjusted up to 256 dwords (1024 bytes). The Host will select the optimal length based on a

number of factors including the system environment for the PCI Bus, the number of HDLC channels

being used, and the trade off between channel latency and bus efficiency.

00 = burst length maximum is 32 dwords

01 = burst length maximum is 64 dwords

10 = burst length maximum is 128 dwords

11 = burst length maximum is 256 dwords

Bit 6 / PCI Bus Orientation (PBO).

This bit selects whether HDLC packet data on the PCI Bus will operate in either Little Endian format or

Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address

while Big Endian places the least significant byte at the highest address. This bit setting only affects

HDLC data on the PCI Bus. All other PCI Bus transactions to the internal device configuration registers,

PCI configuration registers, and Local Bus, are always in Little Endian format.

0 = HDLC Packet Data on the PCI Bus is in Little Endian format

1 = HDLC Packet Data on the PCI Bus is in Big Endian format

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