DS3134 datasheet(78/203 Pages) DALLAS

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DS3134

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SECTION 6: HDLC

6.1 GENERAL DESCRIPTION

The DS3134 contains two different types of HDLC controllers. Each port has a Slow HDLC Engine (type

#1) associated with it that can operate in either a channelized mode up to 8.192 Mbps or an unchannelized

mode at rates up to 10 Mbps. Ports 0 and 1 also have associated with them, an additional Fast HDLC

Engine (type #2) that is capable of operating in only an unchannelized fashion up to 52 Mbps. Via the

Layer One registers (see Section 5.2), the Host will determine which type of HDLC controller will be

used on a Port and if the HDLC controller is to be operated in either a channelized or unchannelized

mode. If the HDLC controller is to be operated in the channelized mode, then the Layer One registers

(see Section 5.3) will also determine which HDLC channels are associated with which DS0 channels. If

the Fast HDLC Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC

Channel 2 will be assigned to the Fast HDLC Engine on Port 1 if it is enabled.

The HDLC controllers are capable of handling all the normal real-time tasks required. Table 6.1B lists all

of the functions supported by the Receive HDLC and Table 6.1C lists all of the functions supported by the

Transmit HDLC. Each of the 256 HDLC channels within Chateau are configured by the Host via the

Receive HDLC Channel Definition (RHCD) and Transmit Channel Definition (THCD) registers. There

is a separate RHCD and THCD register for each HDLC channel. The Host can access the RHCD and

THCD registers indirectly via the RHCDIS indirect select and THCDIS indirect select registers. See

Section 6.2 for details.

On the receive side, when the HDLC Block is processing a packet, one of the outcomes shown in

Table 6.1A will occur. For each packet, one of these outcomes will be reported in the Receive Done

Queue Descriptor (see Section 8.1.4 for details).

On the transmit side, when the HDLC Block is

processing a packet, an error in the PCI Block (parity or target abort) or transmit FIFO underflow will

cause the HDLC Block to send an Abort sequence (8 ones in a row) followed continuously by the selected

Interfill (either 7Eh or FFh) until the HDLC channel is reset by the transmit DMA Block (see Section

8.2.1 for details). This same sequence of events will occur even if the transmit HDLC channel is being

operated in the transparent mode. In the transparent mode, when the FIFO empties the device will send

either 7Eh or FFh.

Receive HDLC Packet Processing Outcomes Table 6.1A

Outcome

Criteria

EOF / Normal

Packet

Integral number of packets > min. & < max. is received & CRC is okay

EOF / Bad FCS

Integral number of packets > min. & < max. is received & CRC is bad

Abort Detected

Seven or more ones in a row detected

EOF / Too Few

Bytes

Less than 4 or 6 bytes received

Too Many Bytes

Greater than the packet maximum is received (if detection enabled)

EOF / Bad # of Bits

Not an integral number of bytes received

FIFO Overflow

Tried to write a byte into an already full FIFO

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