DS3134 datasheet(138/203 Pages) DALLAS

138 / 203 page

DS3134

138 of 203

The DMA also checks the Transmit Done Queue Host Read Pointer to make sure that an overflow does

not occur. If this does occur, then the DMA will set the Status Bit for Transmit DMA Done Queue Write

Error (TDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue nor will

it increment the Write Pointer. In such a scenario, information on transmitted packets will be lost and

unrecoverable. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See

Section 4 for more details.

Done Queue Burst Writing

The DMA has the ability to write to the Done Queue in bursts. This allows for a more efficient use of the

PCI Bus. The DMA can hand off descriptors to the Done Queue in-groups rather than one at a time,

freeing up the PCI Bus for more time critical functions.

Internal to the device there is a FIFO that can store up to 8 Done Queue Descriptors (8 dwords since each

descriptor occupies one dword). The Host must configure the FIFO for proper operation via the Transmit

DMA Queues Control (TDMAQ) register (see below).

When enabled via the Transmit Done Queue FIFO Enable (TDQFE) bit, the Done Queue FIFO will not

write to the Done Queue until it reaches the High Water Mark. When the Done Queue FIFO reaches the

High Water Mark (which is six descriptors), it will attempt to empty the Done Queue FIFO by burst

writing to the Done Queue. Before it writes to the Done Queue, it checks (by examining the Transmit

Done Queue Host Read Pointer) to make sure that the Done Queue has enough room to empty the Done

Queue FIFO. If the Done Queue does not have enough room, then it will only burst write enough

descriptors to keep from overflowing the Done Queue. If the FIFO detects that there is no room for any

descriptors to be written, then it will set the Status Bit for Transmit DMA Done Queue Write Error

(TDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue nor will it

increment the Write Pointer. In such a scenario, information on transmitted packets will be lost and

unrecoverable. If the Done Queue FIFO can write descriptors to the Done Queue, then it will burst write

them, increment the write pointer, and set the Status Bit for Transmit DMA Done Queue Write (TDQW)

in the Status Register for DMA (SDMA). See Section 4 for more details on Status bits.

Done Queue FIFO Flush Timer

To make sure that the Done Queue FIFO does get flushed to the Done Queue on a regular basis, the

Transmit Done Queue FIFO Flush Timer (TDQFFT) is used by the DMA to determine the maximum wait

time in between writes. The TDQFFT is a 16-bit programmable counter that is decremented every PCLK

divided by 256. It is only monitored by the DMA when the Transmit Done Queue FIFO is enabled

(TDQFE = 1). For a 33 MHz PCLK, the timer is decremented every 7.76 us and for a 25 MHz clock it is

decremented every 10.24 us. Each time the DMA writes to the Done Queue it resets the timer to the

count placed into it by the Host. On initialization, the Host will set a value into the TDQFFT that

indicates the maximum time the DMA should wait in between writes to the Done Queue. For example,

with a PCLK of 33 MHz, the range of wait times are from 7.8 us (RDQFFT = 0001h) to 508 ms

(RDQFFT = FFFFh) and PCLK of 25 MHz, the wait times range from 10.2 us (RDQFFT = 0001h) to

671 ms (RDQFFT = FFFFh).

DS3134 датащи(PDF) 138 Page - Dallas Semiconductor