DS89C430 datasheet(42/48 Pages) DALLAS

42 / 48 page

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

42 of 48

Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is

selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation

when a qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation.

It is possible to enable a receive function on a serial port when incoming data is not present and then change to the

higher divide ratio. An inactive serial port receive/transmission mode requires the receive input pin to remain high

and all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the

clock-divide control bits from a divide by 1 to a 1024 divide ratio. In the case when the serial port is being used to

receive or transmit data, it is very important to validate an attempted change in the clock-divide control bits (read

CD1 and CD0 to verify write was allowed) before proceeding with low-power program functions.

Table 14. Effect of Clock Mode on Timer Operation (In Number of Oscillator Clocks)

OSC CYCLES PER

TIMERS 0, 1, 2 CLOCK

OSC CYCLES PER

TIMER 2 CLOCK

TxMH,TxM

BAUD RATE

GENERATION

OSC CYCLES PER

SERIAL PORT CLOCK

MODE 0

OSC CYCLES PER

SERIAL PORT CLOCK

MODE 2

4X/

2X, CD1,

CD0

OSC CYCLES

PER MACHINE

CYCLE

T2MH,T2M = xx

SM2 = 0

SM2 = 1

SMOD = 0

SMOD = 1

100

0.25

000

0.5

x01

1 (reserved)

x10

1 (default)

x11

1024

12,288

4096

1024

2048

12,288

4096

65,536

32,768

x = Don’t care.

Ring Oscillator

When the system is in stop mode the crystal is disabled. When stop mode is removed, the crystal requires a period

of time to start up and stabilize. To allow the system to begin immediate execution of software following the

removal of the stop mode, the ring oscillator is used to supply a system clock until the crystal startup time is

satisfied. Once this time has passed, the ring oscillator is switched off and the system clock is switched to the

crystal oscillator. This function is programmable and is enabled by setting the RGSL bit (EXIF.1) to logic 1. When it

is logic 0, the processor delays software execution until after the 65,536 crystal clock periods. To allow the

processor to know whether it is being clocked by the ring or by the crystal oscillator, an additional bit—RGMD—

indicates which clock source is being used. When the processor is running from the ring, the clock-divide control

bits (CD1 and CD0 in the PMR register) are locked into the divide-by-1 mode (CD1:CD0 = 10b). The clock-divide

control bits cannot be changed from this state until after the system clock transitions to the crystal oscillator

(RGMD = 0).

Note: The watchdog is connected to the crystal oscillator and continues to run at the external clock rate. The ring

oscillator does not drive it.

Idle Mode

Idle mode suspends the processor by holding the program counter in a static state. No instructions are fetched and

no processing occurs. Setting the IDLE bit (PCON.0) to logic 1 invokes idle mode. The instruction that executes

this step is the last instruction prior to freezing the program counter. Once in idle mode, all resources are

preserved, but all peripheral clocks remain active and the timers, watchdog, serial ports, and power monitor

functions continue to operate, so that the processor can exit the idle mode using any interrupt sources that are

enabled. The oscillator-detect circuit also continues to function when enabled. The IDLE bit is cleared automatically

once the idle mode is exited. On returning from the interrupt vector using the RETI instruction, the next address is

the one that immediately follows the instruction that invoked the idle mode. Any reset of the processor also

removes the idle mode.

DS89C430 датащи(PDF) 42 Page - Dallas Semiconductor

DS89C430 датащи(HTML) 42 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL