DS89C430 datasheet(13/48 Pages) DALLAS

13 / 48 page

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

13 of 48

PIN DESCRIPTION (continued)

PDIP

PLCC

TQFP

NAME

FUNCTION

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate

functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The

reset condition of port 1 is with all bits at logic 1. In this state, a weak pullup holds the port

high. This condition also serves as an input state, since any external circuit that writes to

the port overcomes the weak pullup. When software writes a 0 to any port pin, the

DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on until either

a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong

transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary

strong driver turns off, the port again becomes the output high (and input) state. The

alternate functions of port 1 are as follows:

PORT

ALTERNATE

FUNCTION

P1.0

External I/O for Timer/Counter2

P1.1

T2EX

Timer 2 Capture/Reload Trigger

P1.2

RXD1

Serial Port 1 Receive

P1.3

TXD1

Serial Port 1 Transmit

P1.4

INT2

External Interrupt 2 (Positive Edge Detect)

P1.5

INT3

External Interrupt 3 (Negative Edge Detect)

P1.6

INT4

External Interrupt 4 (Positive Edge Detect)

P1.7

INT5

External Interrupt 5 (Negative Edge Detect)

P2.0 (A8)

P2.1 (A9)

P2.2(A10)

P2.3(A11)

P2.4(A12)

P2.5(A13)

P2.6(A14)

P2.7(A15)

Port 2 (A8–A15), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset condition of port 2

is logic high. In this state, a weak pullup holds the port high. This condition also serves as

an input mode, since any external circuit that writes to the port overcomes the weak

pullup. When software writes a 0 to any port pin, the DS89C430/DS89C440/DS89C450

activate a strong pulldown that remains on until either a 1 is written or a reset occurs.

Writing a 1 after the port has been at 0 causes a strong transition driver to turn on,

followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the

port again becomes both the output high and input state. As an alternate function, port 2

can function as the MSB of the external address bus when reading external program

memory and read/write external RAM or peripherals. In page mode 1, port 2 provides both

the MSB and LSB of the external address bus. In page mode 2, it provides the MSB and

data.

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate

functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and

RD and

WR strobes. The reset condition of port 3 is with all bits at a logic 1. In this state, a weak

pullup holds the port high. This condition also serves as an input mode, since any external

circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any

port pin, the DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on

until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes

a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the

momentary strong driver turns off, the port again becomes both the output high and input

state. The alternate modes of port 3 are as follows:

PORT

ALTERNATE

FUNCTION

P3.0

RXD0

Serial Port 0 Receive

P3.1

TXD0

Serial Port 0 Transmit

P3.2

INT0

External Interrupt 0

P3.3

INT1

External Interrupt 1

P3.4

Timer 0 External Input

P3.5

Timer 1 External Input

P3.6

External Data Memory Write Strobe

P3.7

External Data Memory Read Strobe

External Access. Allows selection of internal or external program memory. Connect to

ground to force the DS89C430/DS89C440/DS89C450 to use an external memory program

memory. The internal RAM is still accessible as determined by register settings. Connect

to VCC to use internal flash memory.

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