DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

36 of 48

Interrupt Priority

There are five levels of interrupt priority: Level 4 to 0. The highest interrupt priority is level 4, which is reserved for

the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each

interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is

enabled. All interrupts also have a natural hierarchy. In this manner, when a set of interrupts has been assigned the

same priority, a second hierarchy determines which interrupt is allowed to take precedence. The natural hierarchy

is determined by analyzing potential interrupts in a sequential manner with the order listed in Table 11.

The processor indicates that an interrupt condition occurred by setting the respective flag bit. This bit is set

regardless of whether the interrupt is enabled or disabled. Unless marked in Table 11, all these flags must be

cleared by software.

Table 11. Interrupt Summary

INTERRUPT

VECTOR

NATURAL ORDER

FLAG

ENABLE

PRIORITY CONTROL

Power Fail

33h

0 (Highest)

PFI (WDCON.4)

EPFI(WDCON.5)

N/A

External Interrupt 0

03h

1

IE0 (TCON.1) (Note 1)

EX0 (IE.0)

LPX0 (IP0.0);

MPX0 (IP1.0)

Timer 0 Overflow

0Bh

2

TF0 (TCON.5) (Note 2)

ET0 (IE.1)

LPT0 (IP0.1);

MPT0 (IP1.1)

External Interrupt 1

13h

3

IE1 (TCON.3) (Note 1)

EX1 (IE.2)

LPX1 (IP0.2);

MPX1 (IP1.2)

Timer 1 Overflow

1Bh

4

TF1 (TCON.7) (Note 2)

ET1 (IE.3)

LPT1 (IP0.3);

MPT1 (IP1.3)

Serial Port 0

23h

5

RI_0 (SCON0.0);

TI_0 (SCON0.1)

ES0 (IE.4)

LPS0 (IP0.4);

MPS0 (IP1.4)

Timer 2 Overflow

2Bh

6

TF2 (T2CON.7);

EXF2 (T2CON.6)

ET2 (IE.5)

LPT2 (IP0.5);

MPT2 (IP1.5)

Serial Port 1

3Bh

7

RI_1 (SCON1.0);

TI_1 (SCON1.1)

ES1 (IE.6)

LPS1 (IP0.6);

MPS1 (IP1.6)

External Interrupt 2

43h

8

IE2 (EXIF.4)

EX2 (EIE.0)

LPX2 (EIP0.0);

MPX2 (EIP1.0)

External Interrupt 3

4Bh

9

IE3 (EXIF.5)

EX3 (EIE.1)

LPX3 (EIP0.1);

MPX3 (EIP1.1)

External Interrupt 4

53h

10

IE4 (EXIF.6)

EX4 (EIE.2)

LPX4 (EIP0.2);

MPX4 (EIP1.2)

External Interrupt 5

5Bh

11

IE5 (EXIF.7)

EX5 (EIE.3)

LPX5 (EIP0.3);

MPX5 (EIP1.3)

Watchdog

63h

12 (Lowest)

WDIF (WDCON.3)

EWDI (EIE.4)

LPWDI (EIP0.4);

MPWDI (EIP1.4)

Note 1: If the interrupt is edge triggered, the flag is cleared automatically by hardware when the service routine is vectored to. If the interrupt

is level triggered, the flag follows the state of the pin.

Note 2: The flag is cleared automatically by hardware when the service routine is vectored to.