DS89C430 datasheet(23/48 Pages) DALLAS

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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Note: The read/write accessibility of the flash memory during in-application programming is not affected by the

state of the lock bits. However, the lock bits do affect the read/write accessibility in ROM loader and parallel

programming modes.

In-Application Programming by User Software

The DS89C430 supports in-application programming of on-chip flash memory by user software. In-application

programming is initiated by writing a flash command into the flash control (FCNTL:D5h) register to enable the flash

memory for erase/program/verify operations. Address and data are input into the MMU through the flash data

(FDATA:D6h) register. The flash command also enables read/write accesses to the FDATA. The MMU’s sequencer

provides the operation sequences and control functions to the flash memory. The MMU is designed to operate

independently from the processor, except for read/write access to the SFRs.

Only the upper bank of the on-chip program memory can be in-application programmed by the user software. The

lower bank of the on-chip program memory contains system hardware-dependent codes that are crucial to system

operation and should not be altered during in-application programming.

All flash operations are self-timed. The user software can monitor the progress of an erase or programming

operation through the flash busy (FBUSY;FCNTL.7) bit with a reset value at logic 1. A selected operation

automatically starts when required data is written to the FDATA SFR. The MMU clears the FBUSY bit to indicate

the start of a write/erase operation. The FBUSY bit may not change state for up to 1

ms after the operation is

requested. During this time, the application should poll the status of the FBUSY bit waiting for it to change state.

This bit is held low until either the end of the operation or until an error indicator is returned. A flash operating

failure terminates the current operation and sets the flash error flag (FERR;FCNTL.6) to logic 1. Both the busy and

error flags are read-only bits.

Read/write access during in-application programming is not affected by the state of the lock bits.

A sample programming sequence for a "write upper program memory bank" is shown below. The command must be

reentered each time an operation is requested, i.e., it is not permissible to issue the “write upper program memory

bank” command once and then repeatedly load address and data values to program a block of memory.

1. Make sure the

FBUSY bit is 1 to indicate flash MMU is idle.

2. Write 0Bh to the FCNTL register using the timed access sequence.

3. Write address_MSB to the FDATA register.

4. Write address_LSB to the FDATA register.

5. Write data_value to the FDATA register.

6. Make sure the

FBUSY bit is 0 to indicate programming has started.

7. Wait for

FBUSY bit to return to 1 to indicate end of programming operation.

8. Make sure FERR is 0 to indicate no programming error.

The flash command (FC3–FC0;FCNTL.3:0) bits provide flash commands as listed in Table 4.

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