DS89C430 datasheet(41/48 Pages) DALLAS

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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

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External/Hardware Reset

A hardware reset can be initiated by asserting the RST pin high for at least three external clock cycles while the

external clock is running. The reset is asserted immediately.

When the RST pin is taken to a logic low, the microcontroller exits the reset state within a delay that depends on

the state of the flash memory at the time the reset was asserted. If a flash write or erase operation was in progress,

the reset state is a 4ms maximum. If no flash write or erase operations were in progress, there is a delay of 90

external clock cycles. Operation resumes at address 0000h. If taking RST to a logic low causes the device to exit

stop mode, an additional delay of 65,536 clock cycles is experienced before operation begins.

Reset Output

If a reset is caused by a power-fail reset, a watchdog timer reset, or an internal system reset, a logic high output-

reset pulse is also generated at the bidirectional RST pin. This reset pulse is asserted as long as an internal reset

is asserted. Although the microcontroller generates its own power-on delay for crystal warmup, legacy designs may

employ an external RC circuit. Large values of “C” may load the pin enough that the RST output may not achieve a

logic high, but the state of the external RST pin does not affect the internal reset condition.

Oscillator-Fail Detect and Reset

The DS89C430 incorporates an oscillator-fail-detect circuit that, when enabled, causes a reset if the crystal

oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the

OFDE (PCON.4) bit to logic 1 enables the circuit. The OFDE bit is only cleared from logic 1 to logic 0 by a power-

fail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to logic 1. This flag is

cleared by software or power-on reset. This circuit does not force a reset when the oscillator is stopped by the

software-enabled stop mode.

Power-Management Mode

The power-management mode offers a software-controllable power-saving scheme by providing a reduced

instruction cycle speed, which allows the microcontroller to continue operating while using an internally divided

version of the clock source to save power. Power-management mode is invoked by software setting the clock-

divide control bits CD1 and CD0 (PMR.7–6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for

one machine cycle. On all forms of reset, the clock-divide control bits default to 10b, which selects one oscillator

cycle per machine cycle.

Since the clock speed choice affects all functional logic, including timers, several hardware switchback features

allow the clock speed to automatically return to the divide-by-1 mode from a reduced cycle rate. Setting the SWB

(PMR.5) bit to 1 in software enables this switchback function.

When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the system

forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an

externally enabled (and allowed by nesting priorities) interrupt. The switchback occurs whenever one of the two

following conditions occurs. The first switchback condition is initiated by the detection of a low on either

INT0, INT1,

INT3, or INT5 or a high on INT2 or INT4 when the respective pin has been programmed and allowed (by nesting

priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to

receive data and is found to have an active-low transition on the respective receive-input pin. Serial port transmit

activity also forces a switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is

independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024

mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by-

1 mode. Note also that the switchback interrupt relationship requires that the respective external interrupt source is

allowed to actually generate an interrupt, as defined by the priority of the interrupt and the state of the nested

interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting

of serial port enable. Disabling external interrupts and serial port receive/transmission mode disables the automatic

switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of

the clock divider are disabled. All other clock modes ignore the switchback relationship and are unaffected by

interrupts and serial port activity.

The basic divide-by-12 mode for the timers (TxMH, TxM = 00b) as well as the divide by 32 and 64 for mode 2 on

the serial ports has been maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1.

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