DS89C430 datasheet(37/48 Pages) DALLAS

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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Timer/Counters

The DS89C430 incorporates three 16-bit timers. All three timers can be used as either counters of external events,

where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 12

summarizes the timer functions.

Timers 0 and 1 both have three modes of operations. They can each be used as a 13-bit timer/counter, a 16-bit

timer/counter, or an 8-bit timer/counter with autoreload. Timer 0 has a fourth operating mode as two 8-bit

timer/counters without autoreload. Each timer can also be used as a counter of external pulses on the

corresponding T0/T1 pin for 1-to-0 transitions. The timer mode (TMOD) register controls the mode of operation.

Each timer consists of a 16-bit register in 2 bytes, which can be found in the SFR map as TL0, TH0, TL1, and TH1.

The timer control (TCON) register enables timers 0 and 1.

Table 12. Timer Functions

FUNCTIONS

TIMER 0

TIMER 1

TIMER 2

Timer/Counter

13/16/8*/2x8 bit

13/16/8* bit

16 bit

Timer with Capture

Yes

External Control Pulse Counter

Yes

Up/Down Autoreload Timer/Counter

Yes

Baud Rate Generator

Yes

Timer Output Clock Generator

Yes

*8-bit timer/counter includes autoreload feature. 2x8-bit mode does not.

Each timer has a selectable time base (Table 14). Following a reset, the timers default to divide by 12 to maintain

drop-in compatibility with the 8051. If timer 2 is used as a baud rate generator or clock output, its time base is fixed

at divide by 2, regardless of the setting of its timer mode bits.

Timer 2 is a true 16-bit timer/counter that, with a 16-bit capture (RCAP2L and RCAP2H) register, is able to provide

some unique functions like up/down autoreload timer/counter and timer output-clock generation. Timer 2 (registers

TL2 and TH2) is enabled by the T2CON register. Its mode of operation is selected by the T2MOD register.

For operation details, refer to Section 11: Programmable Timers in the Ultra-High-Speed Flash Microcontroller

User’s Guide.

Timed Access

The timed-access function prevents an errant CPU from making accidental changes to certain SFR bits that are

considered vital to proper system operation. This is achieved by using software control when accessing the

following SFR control bits:

SFR

BIT

FUNCTION

WDCON.0

RWT

Reset Watchdog Timer

WDCON.1

EWT

Watchdog Reset Enable

WDCON.3

WDIF

Watchdog Interrupt Flag

WDCON.6

POR

Power-On Reset Flag

EXIF.0

BGS

Bandgap Select

ACON.5

PAGES0

Page Mode Select Bit 0

ACON.6

PAGES1

Page Mode Select Bit 1

ACON.7

PAGEE

Page Mode Enable

ROMSIZE.0

RMS0

Program Memory Size Select Bit 0

ROMSIZE.1

RMS1

Program Memory Size Select Bit 1

ROMSIZE.2

RMS2

Program Memory Size Select Bit 2

ROMSIZE.3

PRAME

Program RAM Enable

FCNTL.0

FC0

Flash Command Bit 0

FCNTL.1

FC1

Flash Command Bit 1

FCNTL.2

FC2

Flash Command Bit 2

FCNTL.3

FC3

Flash Command Bit 3

Before these bits can be altered, the processor must execute the timed-access sequence. This sequence consists

of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three

machine cycles. This timed sequence of steps allows any of the timed access-protected SFR bits to be altered

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