DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Table 2. SFR Reset Value (continued)

REGISTER

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TL2

CCh

0

0

0

0

0

0

0

0

TH2

CDh

0

0

0

0

0

0

0

0

PSW

D0h

0

0

0

0

0

0

0

0

FCNTL

D5h

1

0

1

1

0

0

0

0

FDATA

D6h

0

0

0

0

0

0

0

0

WDCON

D8h

0

Special

0

Special

0

Special

Special

0

ACC

E0h

0

0

0

0

0

0

0

0

EIE

E8h

1

1

1

0

0

0

0

0

B

F0h

0

0

0

0

0

0

0

0

EIP1

F1h

1

1

1

0

0

0

0

0

EIP0

F8h

1

1

1

0

0

0

0

0

Note: Consult the Ultra-High-Speed Flash Microcontroller User’s Guide for more information about the bits marked “Special.”

Memory Organization

There are three distinct memory areas in the DS89C430: scratchpad registers, program memory, and data

memory. The registers are located on-chip but the program and data memory spaces can be on-chip, off-chip, or

both. The DS89C430/DS89C440/DS89C450 have 16kB/32kB/64kB of on-chip program memory, respectively,

implemented in flash memory and also have 1kB of on-chip data memory space that can be configured as program

space using the PRAME bit in the ROMSIZE feature. The DS89C430 uses a memory-addressing scheme that

separates program memory from data memory. The program and data segments can be overlapped since they are

accessed in different manners. If the maximum address of on-chip program or data memory is exceeded, the

DS89C430 performs an external memory access using the expanded memory bus. The

PSEN signal goes active

low to serve as a chip enable or output enable when performing a code fetch from external program memory.

MOVX instructions activate the

RD or WR signal for external MOVX data memory access. The program memory

ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory.

This allows the DS89C430 to act as a bootloader for an external memory. It also enables the use of the

overlapping external program spaces. The lower 128 bytes of on-chip flash memory—if ROMSIZE is greater than

0—are used to store reset and interrupt vectors. 256 bytes of on-chip RAM serve as a register area and program

stack, which are separated from the data memory.

Register Space

Registers are located in the 256 bytes of on-chip RAM labeled “internal registers” (Figure 6), which can be divided

into two sub areas of 128 bytes each. Separate classes of instructions are used to access the registers and the

program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map.

Indirect addressing is used to access the upper 128 bytes of scratchpad RAM, while the SFR area is accessed

using direct addressing. The lower 128 bytes can be accessed using direct or indirect addressing.

There are four banks of eight working registers in the lower 128 bytes of scratchpad RAM. The working registers

are general-purpose RAM locations that can be addressed within the selected bank by any instructions that use

R0–R7. The register bank selection is controlled through the program status register in the SFR area. The contents

of the working registers can be used for indirect addressing of the upper 128 bytes of scratchpad RAM.

Individually addressable bits in the RAM and SFR areas support Boolean operations. In the scratchpad RAM area,

registers 20h–2Fh are bit addressable by software using Boolean operation instructions.

Another use of the scratchpad RAM area is for the stack. The stack pointer, contained in the SFRs, is used to

select storage locations for program variables and for return addresses of control operations.