DS89C430 datasheet(12/48 Pages) DALLAS

12 / 48 page

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

12 of 48

PIN DESCRIPTION

PDIP

PLCC

TQFP

NAME

FUNCTION

12, 44

6, 38

VCC

+5V

1, 22, 23,

16, 17, 28,

GND

Logic Ground

RST

External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to

recognize external active-high reset inputs. The pin also employs an internal pulldown

resistor to allow for a combination of wire-ORed external reset sources. An RC is not

required for power-up, as the device provides this function internally.

XTAL1

XTAL2

Crystal Oscillators. These pins provide support for fundamental-mode parallel-resonant

AT-cut crystals. XTAL1 also acts as an input if there is an external clock source in place of

a crystal. XTAL2 serves as the output of the crystal amplifier.

PSEN

Program Store Enable. This signal is commonly connected to optional external program

memory as a chip enable.

PSEN provides an active-low pulse and is driven high when

external program memory is not being accessed. In one-cycle page mode 1,

PSEN

remains low for consecutive page hits.

ALE/

PROG

Address Latch Enable. This signal functions as a clock to latch the external address LSB

from the multiplexed address/data bus on Port 0. This signal is commonly connected to the

latch enable of an external 373-family transparent latch. In default mode, ALE has a pulse

width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE

pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE

is high when using the EMI reduction mode and during a reset condition. ALE can be

enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON

during external memory accesses. As an alternate mode, this pin (

PROG) is used to

execute the parallel program function.

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an

alternate function, Port 0 can function as the multiplexed address/data bus to access off-

chip memory. During the time when ALE is high, the LSB of a memory address is

presented. When ALE falls to logic 0, the port transitions to a bidirectional data bus. This

bus is used to read external program memory and read/write external RAM or peripherals.

When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset

condition of port 0 is tri-state. Pullup resistors are required only when using port 0 as an

I/O port.

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