DS89C430 datasheet(29/48 Pages) DALLAS

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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

29 of 48

Page Mode, External Memory Cycle

Page mode retains the basic circuitry requirement for an original 8051 external memory interface, but alters the

configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles.

Additionally, the functions of ALE and

PSEN are altered to support this mode of operation.

Setting the PAGEE (ACON.7) bit to logic 1 enables page mode. Clearing the PAGEE bit to logic 0 disables the

page mode and the external bus structure defaults to the original 8051 expanded bus configuration (nonpage

mode). The DS89C430 supports page mode in two external bus structures. The logic value of the page-mode-

select bits in the ACON register determines the external bus structure and the basic memory cycle in number of

system clocks. Table 6 summarizes this option. The first three selections use the same bus structure but with

different memory cycle time. Setting the select bits to 11b selects another bus structure. Write access to the ACON

Table 6. Page Mode Select

CLOCKS PER MEMORY CYCLE

PAGES1:PAGES0

PAGE-HIT

PAGE-MISS

EXTERNAL BUS STRUCTURE

P0: Primary data bus.

P2: Primary address bus, multiplexing both the upper byte and

lower byte of address.

P0: Primary data bus.

P2: Primary address bus, multiplexing both the upper byte and

lower byte of address.

P0: Primary data bus.

P2: Primary address bus, multiplexing both the upper byte and

lower byte of address.

P0: Lower address byte.

P2: The upper address byte is multiplexed with the data byte.

Note: This setting affects external code fetches only; accessing

the external data memory requires four clock cycles, regardless

of page hit or miss.

The first page mode’s (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both

the most significant byte and least significant byte of the address for each external memory cycle) and P0 is used

as the primary data bus. During external code fetches, P0 is held in a high-impedance state by the processor. Op

codes are driven by the external memory onto P0 and latched at the end of the external fetch cycle at the rising

edge of

PSEN. During external data read/write operations, P0 functions as the data I/O bus. It is held in a high-

impedance state for external reads from data memory and driven with data during external writes to data memory.

A page miss occurs when the most significant byte of the subsequent address is different from the last

address. The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.

A page hit occurs when the most significant byte of the subsequent address does not change from the last

address. The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.

During a page hit, P2 drives Addr [0–7] of the 16-bit address, while the most significant address byte is held in the

external address latches.

PSEN, RD, and WR strobes accordingly for the appropriate operation on the P0 data bus.

There is no ALE assertion for page hits.

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