TMS320DM641 datasheet(15/171 Pages) TI

15 / 171 page

Device Overview

June 2003 − Revised August 2004

SPRS222C

Device Overview

1.1

Features

D High-Performance Digital Media Processor

(TMS320DM641/TMS320DM640)

− 2.5-, 2-, 1.67-ns Instruction Cycle Time

− 400-, 500-, 600-MHz Clock Rate

− Eight 32-Bit Instructions/Cycle

− 3200, 4000, 4800 MIPS

− Fully Software-Compatible With C64x



D VelociTI.2 Extensions to VelociTI

Advanced Very-Long-Instruction-Word

(VLIW) TMS320C64x

 DSP Core

− Eight Highly Independent Functional

Units With VelociTI.2

 Extensions:

− Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad

8-Bit Arithmetic per Clock Cycle

− Two Multipliers Support

Four 16 x 16-Bit Multiplies

(32-Bit Results) per Clock Cycle or

Eight 8 x 8-Bit Multiplies

(16-Bit Results) per Clock Cycle

− Load-Store Architecture With

Non-Aligned Support

− 64 32-Bit General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

D Instruction Set Features

− Byte-Addressable (8-/16-/32-/64-Bit Data)

− 8-Bit Overflow Protection

− Bit-Field Extract, Set, Clear

− Normalization, Saturation, Bit-Counting

− VelociTI.2

 Increased Orthogonality

D L1/L2 Memory Architecture

− 128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)

− 128K-Bit (16K-Byte) L1D Data Cache

(2-Way Set-Associative)

− 1M-Bit (128K-Byte) L2 Unified Mapped

RAM/Cache

(Flexible RAM/Cache Allocation)

D Endianess: Little Endian, Big Endian

D 32-Bit External Memory Interface (EMIF)

− Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

Synchronous Memories (SDRAM,

SBSRAM, ZBT SRAM, and FIFO)

− 1024M-Byte Total Addressable External

Memory Space

D Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

D 10/100 Mb/s Ethernet MAC (EMAC)

− IEEE 802.3 Compliant

− Media Independent Interface (MII)

− 8 Independent Transmit (TX) Channels

and 1 Receive (RX) Channel

D Management Data Input/Output (MDIO)

D Two Configurable Video Ports (DM641)

D One Configurable Video Port (DM640)

− Providing a Glueless I/F to Common

Video Decoder and Encoder Devices

− Supports Multiple Resolutions and Video

Standards

D VCXO Interpolated Control Port (VIC)

− Supports Audio/Video Synchronization

D Host-Port Interface (HPI) [16-Bit] (DM641)

D Multichannel Audio Serial Port (McASP)

− Four Serial Data Pins

− Wide Variety of I2S and Similar Bit

Stream Format

− Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,

CP-430 Formats

D Inter-Integrated Circuit (I2C) Bus

D Two Multichannel Buffered Serial Ports

D Three 32-Bit General-Purpose Timers

D Eight General-Purpose I/O (GPIO) Pins

D Flexible PLL Clock Generator

D IEEE-1149.1 (JTAG†)

Boundary-Scan-Compatible

D 548-Pin Ball Grid Array (BGA) Package

(GDK Suffix), 0.8-mm Ball Pitch

D 548-Pin Ball Grid Array (BGA) Package

(GNZ Suffix), 1.0-mm Ball Pitch

D 0.13-µm/6-Level Cu Metal Process (CMOS)

D 3.3-V I/O, 1.2-V Internal (-400, -500)

D 3.3-V I/O, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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