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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 48 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 48 Page - Texas Instruments |
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48 / 171 page  Pin Assignments 48 June 2003 − Revised August 2004 SPRS222C Table 1−6. Terminal Functions (Continued) SIGNAL DESCRIPTION IPD/ IPU‡ TYPE† NAME DESCRIPTION IPD/ IPU‡ TYPE† DM640 DM641 EMIFA (32-BIT) − DATA (CONTINUED) AED13 A20 A20 AED12 D20 D20 AED11 B20 B20 AED10 C20 C20 AED9 A21 A21 AED8 D21 D21 AED7 B21 B21 I/O/Z IPU EMIFA external data AED6 C21 C21 I/O/Z IPU EMIFA external data AED5 A23 A23 AED4 C22 C22 AED3 B22 B22 AED2 B23 B23 AED1 A24 A24 AED0 B24 B24 MANAGEMENT DATA INPUT/OUTPUT (MDIO) MDCLK R5 R5 I/O/Z IPD MDIO serial clock input/output (I/O/Z). MDIO P5 P5 I/O/Z IPU MDIO serial data input/output (I/O/Z). VCX0 INTERPOLATED CONTROL PORT (VIC) VDAC AD1 AD1 O/Z IPD VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only]. VIDEO PORTS (VP0 [DM641/DM640] AND VP1 [DM641 ONLY]) STCLK AC1 AC1 I IPD The STCLK signal drives the hardware counter on the video ports. 8-BIT VIDEO PORT 1 (VP1) [DM641 ONLY] VP1D[7] AC8 — Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data input/output VP1D[6]/CLKR1§ AD8 *** Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data input/output (I/O/Z) [default] [DM641 only] VP1D[5]/FSR1§ AC7 *** (I/O/Z) [default] [DM641 only] *** − The DM640 device does not support the VP1 peripheral; therefore, the VP1D[4]/DR1§ AD7 *** I/O/Z IPD *** − The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone peripheral functions, not muxed. VP1D[3]/CLKS1§ AE7 *** I/O/Z IPD McBSP1 peripheral pins are standalone peripheral functions, not muxed. VP1D[2]/DX1§ AC6 *** For more details on the McBSP1 pin functions [for both the DM641 and DM640 devices], see McBSP1 section of this table and the Device VP1D[1]/FSX1§ AD6 *** For more details on the McBSP1 pin functions [for both the DM641 and DM640 devices], see McBSP1 section of this table and the Device Configurations section of this data sheet. VP1D[0]/CLKX1§ AE6 *** Configurations section of this data sheet. VP1CLK1 AF10 — I/O/Z IPD VP1 clock 1 (I/O/Z) VP1CLK0 AF8 — I IPD VP1 clock 0 (I) VP1CTL2 AD5 — VP1 control 2 (I/O/Z) VP1CTL1 AE5 — I/O/Z IPD VP1 control 1 (I/O/Z) VP1CTL0 AF4 — I/O/Z IPD VP1 control 0 (I/O/Z) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
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