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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 46 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 46 Page - Texas Instruments |
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46 / 171 page  Pin Assignments 46 June 2003 − Revised August 2004 SPRS222C Table 1−6. Terminal Functions (Continued) SIGNAL DESCRIPTION IPD/ IPU‡ TYPE† NAME DESCRIPTION IPD/ IPU‡ TYPE† DM640 DM641 EMIFA (32-BIT) − BUS ARBITRATION AHOLDA N22 N22 O IPU EMIFA hold-request-acknowledge to the host AHOLD W24 W24 I IPU EMIFA hold request from the host ABUSREQ P22 P22 O IPU EMIFA bus request output EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL AECLKIN H25 H25 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins. AECLKIN is the default for the EMIFA input clock. AECLKOUT2 J23 J23 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. AECLKOUT1 J26 J26 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. AARE/ ASDCAS/ ASADS/ASRE J25 J25 O/Z IPU EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable • For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. AAOE/ ASDRAS/ ASOE J24 J24 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable AAWE/ ASDWE/ ASWE K26 K26 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable ASDCKE L25 L25 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode). • If SDRAM is not in system, ASDCKE can be used as a general-purpose output. ASOE3 R22 R22 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) AARDY L22 L22 I IPU Asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
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