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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 43 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 43 Page - Texas Instruments |
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43 / 171 page  Pin Assignments 43 June 2003 − Revised August 2004 SPRS222C Table 1−6. Terminal Functions SIGNAL TYPE† IPD/ IPU‡ DESCRIPTION NAME DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN AC2 AC2 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP0[1]§ D6 D6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z). CLKOUT6/GP0[2]§ C6 C6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). CLKMODE1 AE4 AE4 I IPD Clock mode select • Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. CLKMODE0 AA2 AA2 I IPD (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLLV¶ V6 V6 A# PLL voltage supply JTAG EMULATION TMS E15 E15 I IPU JTAG test-port mode select TDO B18 B18 O/Z IPU JTAG test-port data out TDI A18 A18 I IPU JTAG test-port data in TCK A16 A16 I IPU JTAG test-port clock TRST D14 D14 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data sheet. EMU11 D17 D17 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected. EMU10 C17 C17 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected. EMU9 B17 B17 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 D16 D16 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 A17 A17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 C16 C16 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 B16 B16 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 D15 D15 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 C15 C15 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 B15 B15 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 C14 C14 I/O/Z IPU Emulation pin 1|| EMU0 A15 A15 I/O/Z IPU Emulation pin 0|| † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. ¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) || The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k Ω resistor. |
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