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TMS320DM641 датащи(PDF) 36 Page - Texas Instruments

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номер детали TMS320DM641
подробное описание детали  Video/Imaging Fixed-Point Digital Signal Processors
PDF  171 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320DM641 датащи(HTML) 36 Page - Texas Instruments

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Pin Assignments
36
June 2003 − Revised August 2004
SPRS222C
1.9.2
Signal Groups Description
TRST
GP0[7]/EXT_INT7‡
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
NMI
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
RESET
RSV01
RSV02
Clock/PLL
CLKIN
CLKMODE1
CLKMODE0
PLLV
EMU2
EMU3
EMU4
EMU5
GP0
(8-Bit)
General-Purpose Input/Output 0 (GP0) Port
GP0[7]/EXT_INT7‡
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
GP0[3]
CLKOUT6/GP0[2]†
CLKOUT4/GP0[1]†
GP0[0]
CLKOUT6/GP0[2]†
CLKOUT4/GP0[1]†
EMU6
EMU7
EMU8
EMU9
EMU10
These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these
muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured.
For more details, see the Device Configurations section of this data sheet.
†
These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
‡
RSV00
EMU11
RSV92(124)
RSV93(125)
RSV91(123)
Peripheral
Control/Status
TOUT0/MAC_EN
Figure 1−5. CPU and Peripheral Signals



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