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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM641 датащи(PDF) 91 Page - Texas Instruments |
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TMS320DM641 датащи(HTML) 91 Page - Texas Instruments |
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91 / 171 page  Enhanced Direct Memory Access (EDMA) Controller 91 June 2003 − Revised August 2004 SPRS222C Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events† (Continued) EDMA CHANNEL EVENT DESCRIPTION EVENT NAME 36 AREVTO0 McASP0 receive odd event 37 AREVT0 McASP0 receive event 38−43 – None 44 ICREVT0 I2C0 receive event 45 ICXEVT0 I2C0 transmit event 46−47 – None 48 GPINT8 GP0 event 8 49 GPINT9 GP0 event 9 50 GPINT10 GP0 event 10 51 GPINT11 GP0 event 11 52 GPINT12 GP0 event 12 53 GPINT13 GP0 event 13 54 GPINT14 GP0 event 14 55 GPINT15 GP0 event 15 56 VP1EVTYA VP1 Channel A Y event DMA request [For DM641 Only; “None” for DM640] 57 VP1EVTUA VP1 Channel A Cb event DMA request [For DM641 Only; “None” for DM640] 58 VP1EVTVA VP1 Channel A Cr event DMA request [For DM641 Only; “None” for DM640] 59−63 – None † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). |
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