TMS320DM641 datasheet(85/171 Pages) TI

85 / 171 page

Parameter Information

June 2003 − Revised August 2004

SPRS222C

4.1.1.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good

board design practice, such delays must always be taken into account. Timing values may be adjusted by

increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification

(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate

timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature

number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing

differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device

and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time

margin, but also tends to improve the input hold time margins (see Table 4−1 and Figure 4−4).

Figure 4−4 represents a general transfer between the DSP and an external device. The figure also represents

board route delays and how they are perceived by the DSP and the external device.

Table 4−1. Board-Level Timing Example (see Figure 4−4)

NO.

DESCRIPTION

Clock route delay

Minimum DSP hold time

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

ECLKOUTx

(Output from DSP)

ECLKOUTx

(Input to External Device)

Control Signals†

(Output from DSP)

Control Signals

(Input to External Device)

Data Signals‡

(Output from External Device)

Data Signals‡

(Input to DSP)

† Control signals include data for Writes.

‡Data signals are generated during Reads from an external device.

Figure 4−4. Board-Level Input/Output Timings

4.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

TMS320DM641 датащи(PDF) 85 Page - Texas Instruments

TMS320DM641 датащи(HTML) 85 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL