TMS320DM641 datasheet(103/171 Pages) TI

103 / 171 page

Clock PLL

103

June 2003 − Revised August 2004

SPRS222C

Table 4−17. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6†‡§

(see Figure 4−13)

NO.

PARAMETER

−400

−500

−600

UNIT

NO.

PARAMETER

CLKMODE = x1, x6, x12

UNIT

MIN

MAX

tw(CKO6H)

Pulse duration, CLKOUT6 high

3P − 0.7

3P + 0.7

tw(CKO6L)

Pulse duration, CLKOUT6 low

3P − 0.7

3P + 0.7

tt(CKO6)

Transition time, CLKOUT6

† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

§ P = 1/CPU clock frequency in nanoseconds (ns)

CLKOUT6

Figure 4−13. CLKOUT6 Timing

Table 4−18. Timing Requirements for AECLKIN for EMIFA†‡§ (see Figure 4−14)

NO.

−400

−500

−600

UNIT

MIN

MAX

tc(EKI)

Cycle time, AECLKIN

6¶

16P

tw(EKIH)

Pulse duration, AECLKIN high

2.7

tw(EKIL)

Pulse duration, AECLKIN low

2.7

tt(EKI)

Transition time, AECLKIN

tJ(EKI)

Period jitter, AECLKIN

0.02E

† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

§ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

¶ Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based

on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 device, 133-MHz

operation is achievable if the requirements of the EMIF Device Speed section are met. On the 400 and 500 devices, 100-MHz operation is

achievable if the requirements of the EMIF Device Speed section are met.

AECLKIN

Figure 4−14. AECLKIN Timing for EMIFA

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