DP83848JSQSLASHNOPB datasheet(13/84 Pages) TI1

13 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

AC Timing Requirements (continued)

MIN

NOM

MAX

UNIT

T2.15.3

Receive Data Latency

Measurement shown from SFD

bits

10BASE-T RECEIVE TIMING (END OF PACKET) (REFER TO Figure 5-16)

T2.16.1

Carrier Sense Turn Off Delay

µs

10Mb/s HEARTBEAT TIMING (REFER TO Figure 5-17)

T2.17.1

CD Heartbeat Delay

All 10 Mb/s modes

1200

T2.17.2

CD Heartbeat Duration

All 10 Mb/s modes

1000

10 Mb/s JABBER TIMING (REFER TO Figure 5-18)

T2.18.1

Jabber Activation Time

T2.18.2

Jabber Deactivation Time

500

10BASE-T NORMAL LINK PULSE TIMING (REFER TO Figure 5-19)(16)

T2.19.1

Pulse Width

100

T2.19.2

Pulse Period

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (REFER TO Figure 5-20)(16)

T2.20.1

Clock, Data Pulse Width

100

T2.20.2

Clock Pulse to Clock Pulse Period

125

µs

T2.20.3

Clock Pulse to Data Pulse Period

Data = 1

µs

T2.20.4

Burst Width

T2.20.5

FLP Burst to FLP Burst Period

100BASE-TX SIGNAL DETECT TIMING (REFER TO Figure 5-22)(17)

T2.21.1

SD Internal Turnon Time

T2.21.2

SD Internal Turnoff Time

350

µs

100 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 5-22)(18)(19)

T2.22.1

TX_EN to RX_DV Loopback

100 Mb/s internal loopback mode

240

10 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 5-23)(19)

T2.23.1

TX_EN to RX_DV Loopback

10 Mb/s internal loopback mode

µs

RMII TRANSMIT TIMING (REFER TO Figure 5-24)

T2.24.1

X1 Clock Period

50-MHz Reference Clock

T2.24.2

TXD[1:0], TX_EN, Data Setup to X1 rising

T2.24.3

TXD[1:0], TX_EN, Data Hold from X1 rising

T2.24.4

X1 Clock to PMD Output Pair Latency

From X1 Rising edge to first bit of symbol

bits

RMII RECEIVE TIMING (REFER TO Figure 5-25)(20)(21)(22)(23)(24)(25)

T2.25.1

X1 Clock Period

50-MHz Reference Clock

RXD[1:0], CRS_DV, RX_DV, and RX_ER output

T2.25.2

delay from X1 rising

From JK symbol on PMD Receive Pair to initial assertion

T2.25.3

CRS ON delay

18.5

bits

of CRS_DV

From TR symbol on PMD Receive Pair to initial

T2.25.4

CRS OFF delay

bits

deassertion of CRS_DV

From symbol on Receive Pair. Elasticity buffer set to

T2.25.5

RXD[1:0] and RX_ER latency

bits

default value (01)

(16) These specifications represent transmit timings.

(17) The signal amplitude on PMD Input Pair must be TP-PMD compliant.

(18) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during

which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the

initial 550 µs “dead-time”.

(19) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

(20) Per the RMII Specification, output delays assume a 25-pF load.

(21) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle

synchronously at the end of the packet to indicate CRS deassertion.

(22) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.

(23) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(24) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial deassertion of CRS_DV.

(25) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set

to the default value (01).

Specifications

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