DP83848JSQSLASHNOPB datasheet(11/84 Pages) TI1

11 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

5.5

DC Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

PIN TYPES

MIN

TYP

MAX

UNIT

VIH

Input high voltage

Nominal VCC

I I/O

VIL

Input low voltage

I I/O

0.8

IIH

Input high current

VIN = VCC

I I/O

µA

IIL

Input low current

VIN = GND

I I/O

µA

VOL

Output low voltage

IOL = 4 mA

O, I/O

0.4

VOH

Output high voltage

IOH = –4 mA

O, I/O

Vcc – 0.5

VledOL

Output low voltage

IOL = 2.5 mA

LED

0.4

VledOH

Output high voltage

IOH = –2.5 mA

LED

Vcc – 0.5

IOZ

Tri-state leakage

VOUT = VCC

I/O, O

±10

µA

VTPTD_100

100M Transmit voltage

PMD Output

0.95

1.05

VTPTDsym

100M Transmit voltage symmetry

PMD Output Pair

±2%

VTPTD_10

10M Transmit voltage

PMD Output Pair

2.2

2.5

2.8

CIN1

CMOS Input capacitance

COUT1

CMOS Output capacitance

SDTHon

100BASE-TX Signal detect turnon

PMD Input Pair

1000

mV diff pk-

threshold

SDTHoff

100BASE-TX Signal detect turnoff

PMD Input Pair

200

mV diff pk-

threshold

VTH1

10BASE-T Receive Threshold

PMD Input Pair

585

Idd100

100BASE-TX (Full Duplex)

PMD Input Pair

IOUT = 0 mA

(1)

Idd10

10BASE-T (Full Duplex)

Supply

(1)

Refer to application note SNLA089, “Power Measurement of Ethernet Physical Layer Products”

5.6

AC Timing Requirements

MIN

NOM

MAX

UNIT

POWER UP TIMING (REFER TO Figure 5-1)(1)

MDIO is pulled high for 32-bit serial management

Post Power Up Stabilization time prior to MDC

initialization.

T2.1.1

167

preamble for register accesses

X1 Clock must be stable for a minimum of 167 ms at

power up.

Hardware Configuration Pins are described in Section 4.

Hardware Configuration Latch-in Time from power

T2.1.2

X1 Clock must be stable for a minimum of 167 ms at

167

power up.

Hardware Configuration pins transition to output

T2.1.3

drivers

RESET TIMING (REFER TO Figure 5-2)(2)

Post RESET Stabilization time prior to MDC

MDIO is pulled high for 32-bit serial management

T2.2.1

µs

preamble for register accesses

initialization.

Hardware Configuration Latch-in Time from the

T2.2.2

Hardware Configuration Pins are described in Section 4.

µs

Deassertion of RESET (either soft or hard)

Hardware Configuration pins transition to output

T2.2.3

drivers

X1 Clock must be stable for at minimum of 1 µs during

T2.2.4

RESET pulse width

µs

RESET pulse low time.

MII SERIAL MANAGEMENT TIMING (REFER TO Figure 5-3)

T2.3.1

MDC to MDIO (Output) Delay Time

T2.3.2

MDIO (Input) to MDC Setup Time

T2.3.3

MDIO (Input) to MDC Hold Time

T2.3.4

MDC Frequency

2.5

MHz

(1)

In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.

(2)

It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants

in order to latch-in the proper value prior to the pin transitioning to an output driver.

Specifications

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