DP83848JSQSLASHNOPB datasheet(57/84 Pages) TI1

57 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

www.ti.com

SNLS250E – MAY 2008 – REVISED APRIL 2015

6.6.1.2

Extended Registers

6.6.1.2.1 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed

information.

Table 6-18. PHY Status Register (PHYSTS), address 0x10

Bit

Bit Name

Default

Description

RESERVED

0, RO

RESERVED: Write ignored, read as 0.

MDI-X mode

0, RO

MDI-X mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the

PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as

the Auto-MDIX algorithm swaps between MDI and MDI-X configurations.

1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)

Receive Error

0, RO/LH

Receive Error Latch:

Latch

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0).

0 = No receive error event has occurred.

Polarity Status

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read

of the 10BTSCR register, but not upon a read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

False Carrier

0, RO/LH

False Carrier Sense Latch:

Sense Latch

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (address 0x14).

0 = No False Carrier event has occurred.

Signal Detect

0, RO/LL

100Base-TX unconditional Signal Detect from PMD.

Descrambler

0, RO/LL

100Base-TX Descrambler Lock from PMD.

Lock

Page Received

0, RO

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register, but this bit will not be

cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address

0x06, bit 1).

0 = Link Code Word Page has not been received.

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

Remote Fault

0, RO

Remote Fault:

1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by

reset). Fault criteria: notification from Link Partner of Remote Fault through Auto-Negotiation.

0 = No remote fault condition detected.

Jabber Detect

0, RO

Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not

cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

Auto-Neg

0, RO

Auto-Negotiation Complete:

Complete

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.

Loopback Status 0, RO

Loopback:

1 = Loopback enabled.

0 = Normal operation.

Detailed Description

Submit Documentation Feedback

Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB датащи(PDF) 57 Page - Texas Instruments

DP83848JSQ/NOPB датащи(HTML) 57 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL