DP83848JSQSLASHNOPB datasheet(7/84 Pages) TI1

7 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

www.ti.com

SNLS250E – MAY 2008 – REVISED APRIL 2015

SIGNAL

TYPE

PIN #

DESCRIPTION

NAME

MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the

corresponding RXD[3:0].

RX_DV

O, PD

RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid

indication independent of Carrier Sense.

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid

symbol has been detected within a received packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and

RX_ER

S, O, PU

RX_DV is asserted in 100 Mb/s mode.

This pin is not required to be used by a MAC, in either MII or RMII mode, because the Phy is

required to corrupt data on a receive error.

MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25

RXD_0

MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when

RXD_1

RX_DV is asserted.

S, O, PD

RXD_2

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1

RXD_3

clock, 50 MHz.

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100Mb/s mode or 2.5 MHz in 10 Mb/s

mode derived from the 25-MHz reference clock.

TX_CLK

Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for

both transmit and receive.

MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on

TXD[3:0].

TX_EN

I, PD

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to

TXD_0

the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

TXD_1

TXD_2

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous

TXD_3

I, PD

to the 50-MHz reference clock.

4.5

Clock Interface

SIGNAL

TYPE

PIN #

DESCRIPTION

NAME

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848x

and must be connected to a 25-MHz 0.005% (+50 ppm) clock source. The DP83848x supports

either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level

oscillator source connected to pin X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and

must be connected to a 50-MHz 0.005% (+50 ppm) CMOS-level oscillator source.

CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25-

MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator

clock source is used.

4.6

LED Interface

SIGNAL

TYPE

PIN #

DESCRIPTION

NAME

LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is

good.

LED_LINK

S, O, PU

LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status

of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is

active.

SPEED LED: This LED is ON when DP83848x is in 100 Mb/s and OFF when DP83848x is in 10

LED_SPEED

S, O, PU

Mb/s. Functionality of this LED is independent of the mode selected.(1)

(1)

LED_SPEED only exists in the DP83848J/K. DP83848M/T/H has CLK_OUT on pin 21.

Pin Configuration and Functions

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

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