DP83848JSQSLASHNOPB datasheet(29/84 Pages) TI1

29 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

6.3.1.4

Auto-Negotiaion Restart

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart Auto-

Negotiation) of the BMCR to one. If the mode configured by a successful Auto-Negotiation loses a valid

link, then the Auto-Negotiation process will resume and attempt to determine the configuration for the link.

This function ensures that a valid configuration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a management agent, will cause the DP83848x to halt

any transmit data and link pulse activity until the break_link_timer expires (approximately 1500 ms).

Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83848x

will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse)

bursts.

6.3.1.5

Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, Auto-

Negotiation with next page should take approximately 2-3 seconds to complete, depending on the number

of next pages sent.

Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to Auto-

Negotiation.

6.3.2

Auto-MDIX

When enabled, this function uses Auto-Negotiation to determine the proper configuration for transmission

and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The

function uses a random seed to control switching of the crossover circuitry. This implementation complies

with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications.

Auto-MDIX is enabled by default and can be configured through strap or through PHYCR (0x19h) register,

bits [15:14]. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the

MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (0x19h)

NOTE

Auto-MDIX will not work in a forced mode of operation.

6.3.3

LED Interface

The DP83848J/K supports configurable Light Emitting Diode (LED) pins for configuring the link and speed.

The DP83848H/M/T supports a configurable Light Emitting Diode (LED) pin for configuring the link.

Additional configuration of LED_LINK can be achieved using bit [5] of the PHY Control Register (PHYCR)

at register address 19h.

See Table 6-2 for LED Mode selection of DP83848x.

Table 6-2. LED Mode Select for DP83848x

LED_CFG[0]

MODE

LED_LINK

LED_SPEED(1)

(bit 5) or (pin 33)

ON for Good Link

ON in 100Mb/s

OFF for No Link

OFF in 10Mb/s

ON for Good Link

ON in 100Mb/s

BLINK for Activity

OFF in 10Mb/s

(1)

LED_SPEED only supported for DP83848J/K.

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