DP83848JSQSLASHNOPB datasheet(33/84 Pages) TI1

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DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

6.4.2

Reduced MII Interface

The DP83848x incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII

specification (revision 1.2) from the RMII Consortium. This interface may be used to connect PHY devices

to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits

at a time using the 50-MHz RMII_REF clock for both transmit and receive. The following pins are used in

RMII mode:

•

TX_EN

•

TXD[1:0]

•

RX_ER (optional for Mac)

•

CRS_DV

•

RXD[1:0]

•

X1 (RMII Reference clock is 50 MHz)

In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering

receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for

systems which do not require CRS, such as systems that only support full duplex operation. This signal is

also useful for diagnostic testing where it may be desirable to loop Receive RMII data directly to the

transmitter.

Because the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is

sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached

device can sample the data every 10 clocks.

RMII mode requires a 50-MHz oscillator be connected to the device X1 pin. A 50-MHz crystal is not

supported.

To tolerate potential frequency differences between the 50-MHz reference clock and the recovered receive

clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is

programmable to minimize propagation delay based on expected packet size and clock accuracy. This

allows for supporting a range of packet sizes including jumbo frames.

The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the

FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The

following table indicates how to program the elasticity buffer FIFO (in 4-bit increments) based on expected

max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end

Transmitter clock) have the same accuracy.

Table 6-3. Supported Packet Sizes at ±50 ppm and ±100 ppm for Each Clock

START THRESHOLD

RECOMMENDED PACKET SIZE

LATENCY TOLERANCE

RBR[1:0]

at ±50 ppm

at ±100 ppm

1 (4-bits)

2 bits

2400 bytes

1200 bytes

2 (8-bits)

6 bits

7200 bytes

3600 bytes

3 (12-bits)

10 bits

12000 bytes

6000 bytes

0 (16-bits)

14 bits

16800 bytes

8400 bytes

6.4.3

802.3 MII Serial Management Interface

6.4.3.1

Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. The DP83848x implements all the

required MII registers as well as several optional registers. These registers are fully described in

Section 6.6. A description of the serial management access protocol follows.

Detailed Description

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