DP83848JSQSLASHNOPB datasheet(40/84 Pages) TI1

40 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

6.5.1.1.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted pair

cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is

randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and

on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (that is,

continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feed-back shift register (LFSR) with an 11-bit

polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group

encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated

emissions at certain frequencies by as much as 20 dB. The DP83848x uses the PHY_ID (pins PHYAD

[4:0]) to set a unique seed value.

6.5.1.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in

order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unshielded

twisted pair cable.

6.5.1.1.4 Binary to MLT-3 Convertor

The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from

the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary

streams are then fed to the twisted pair output driver which converts the voltage to current and alternately

drives either side of the transmit transformer primary winding, resulting in a MLT-3 signal.

The 100BASE-TX MLT-3 signal sourced by the PMD Out- put Pair common driver is slew rate controlled.

This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant

transition times (3 ns < Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83848x is capable of sourcing only MLT-3

encoded data. Binary output from the PMD Output Pair is not possible in 100 Mb/s mode.

6.5.1.2

100BASE-TX Receiver

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125

Mb/s serial data stream to synchronous 4-bit nibble data that is pro- vided to the MII. Because the

100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC

coupling magnetics.

See Figure 6-6 for a block diagram of the 100BASE-TX receive function. This provides an overview of

each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

•

Analog Front End

•

Digital Signal Processor

•

Signal Detect

•

MLT-3 to Binary Decoder

•

NRZI to NRZ Decoder

•

Serial to Parallel

•

Descrambler

•

Code Group Alignment

•

4B/5B Decoder

•

Link Integrity Monitor

•

Bad SSD Detection

Detailed Description

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

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