DP83848JSQSLASHNOPB datasheet(4/84 Pages) TI1

4 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

Device Comparison

Table 3-1. Device Features(1)

TEMPERATURE RANGE

DEVICE

TEMPERATURE GRADE

MIN

MAX

DP83848J/M

0°C

70°C

Commercial

DP83848K/T

-40°C

85°C

Industrial

DP83848H

-40°C

125°C

Extreme

(1)

Pin 21 is the CLK_OUT pin for the DP83848H/M/T.

Pin Configuration and Functions

The DP83848x pins are classified into the following interface categories (each interface is described in the

sections that follow):

•

Serial Management Interface

•

MAC Data Interface

•

Clock Interface

•

LED Interface

•

Reset

•

Strap Options

•

10/100 Mb/s PMD Interface

•

Special Connections

•

Power Supply Pins

NOTE

Strapping pin option. See Section 4.8 for strap definitions.

All DP83848x signal pins are I/O cells regardless of the particular use. The definitions below define the

functionality of the I/O cells for each pin.

Type: I

Input

Type: O

Output

Type: I/O

Input/Output

Type: OD

Open Drain

Type: PD,PU Internal Pulldown/Pullup

Type: S

Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap

value is to be changed then an external 2.2-k

Ω resistor should be used. See Section 4.8 for

details.)

Pin Configuration and Functions

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

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