UCS2112 datasheet(20/64 Pages) MICROCHIP

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UCS2112

DS20005424B-page 20

 2015 Microchip Technology Inc.

5.1

UCS2112 Power States

Power states are indicators of the device’s current

consumption in the System and the functionality of the

Digital Logic. Table 5-1 details the UCS2112 power

states.

Table 5-2 shows the settings for the various power

states, except Off and Error. If VDD < VDD_TH, the

UCS2112 is in the Off state.

TABLE 5-1:

POWER STATES DESCRIPTION

State

Description

Off

This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is con-

sidered “off”. The UCS2112 will not retain its digital states and register contents nor respond to SMBus/I2C™

communications. The port power switch and bypass switch will be off. See Section 5.1.1 “Off State Operation”.

Sleep

This is the lowest power state available. While in this state, the UCS2112 will retain digital functionality and wake

to respond to SMBus/I2C communications. See Section 5.1.2 “Sleep State Operation”.

Detect

The Detect power state should not be confused with the actual Attach / Removal Detection feature. Detect Power

State is both channels awaiting attachment. This is a lower-current power state. In this state, the device is actively

looking for a portable device to be attached. While in this state, the UCS2112 will retain the configuration and

charge rationing data, but it will not monitor the bus current. SMBus/I2C communications will be fully functional.

See Section 5.1.3 “Detect State Operation”.

Error

This power state is entered when a fault condition exists. Error power state is one or both channels in Fault Han-

dling. This state is updated as Priority One. The Interrupt Status Registers for each channel will update the fault

detected per channel. Only the channel that has detected a Fault will be affected since the other channel can

remain active if no fault is detected. See Section 5.1.5 “Error State Operation”.

Active

Active power State is one, or both channels active and sourcing current to the VBUS Port. This state is updated

as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in

this state, operations include activation of the port power switch, current limiting, and charge rationing. See

Section 5.1.4 “Active State Operation”

TABLE 5-2:

POWER STATES CONTROL SETTINGS

Power

State

PWR_EN1 PWR_EN2 ATT_DET

Portable

Device

Attached

Behavior

Sleep

disabled

N/A

• All switches disabled.

•VBUS will be near ground potential.

• The UCS2112 wakes to respond to SMBus

communications.

Detect

enabled

disabled

enabled

• Automatic transition to Active state when conditions

met for VBUS1(see Section 5.1.3.1 “Automatic

Transition from Detect to Active”

•VBUS2 pins have very low current delivery capability.

disabled

enabled

• Automatic transition to Active state when conditions

met for VBUS2 (see Section 5.1.3.1 “Automatic

Transition from Detect to Active”

•VBUS1 pins have very low current delivery capability.

enabled

• Automatic transition to Active state when conditions

met for both VBUS1 and VBUS2 (see Section 5.1.3.1

“Automatic Transition from Detect to Active”

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